South East Asia Technical Conference on Electronics Assembly

Professional Development Courses
Tuesday, May 8th

Note: Professional Development Courses (PDCs) are not included with two-day conference registration

8:30am - 12:00pm
PDC1 - Understanding Parameters Affecting Barrel Fill in Wave Soldering Process

1:30pm - 5:00pm
PDC2 - Flip Chip, WLCSP, and FOWLP Assembly and Reliability

8:30am - 12:00pm

PDC1 - Understanding Parameters Affecting Barrel Fill in Wave Soldering Process

AF Ng, Techment Consultancy Sdn. Bhd.

Course Description:

Conventional Wave Soldering has been employed for soldering of boards since long time ago. The related manufacturing personnel are well aware of common encumbering defects happen erratically with this process. Some of these defects encountered daily are bridging, solder skips, solder voids and insufficient barrel fill or hole-fill. Many of us would agree that we are still facing challenges on one of the common defects – poor barrel fill. The problem is confounded with currently High density/Multilayer thick PCB and applying Lead-free soldering. It is important for the Engineering personnel to understand the root causes of the defect, as it can be contributed by factors from board design, material procurement to equipment setting and maintenance. With these numerous factors implicating, the engineers involved must be equipped with sufficient knowledge on soldering fundamentals, laminate composition, thermal demands, design geometry, wetting mechanism during wave contact and equipment maintenance. Commonly, many engineers just adopt recommendations based on DOE results and hoping to get consistent good barrel fill, but mostly to their disappointment due to erratic parameter shift. Many engineers approach the problem by tweaking process parameters on fluxing, preheating, solder pot temperature, wave height adjustment and others, it merely be just a containment and not able to achieve consistent good barrel fill. We need a practical approach in tackling this vexing problem. To do that, one needs to know the fundamentals of wettability involving molten solder. The molten solder wicks up the barrel depend critically on the surface tensions of molten solder in relation to the solder interface with component terminals and copper plated holes. Upon discovering of the root causes, then, appropriate engineering solutions are to be implemented, be it equipment upgrade, board re-design, process adjustment or material changes. The course aims to provide a concise description of these factors through simplified notes, shared experiences and interaction in class.

AF Ng, Techment Consultancy Sdn. Bhd. About the Instructor:

Ah Feau Ng, a Principal Consultant with TechMent Consultancy, has assisted many clients achieved successes in their manufacturing yield and quality improvement. He has developed extensively on-site training programs for organizations in Electronics Industry, majoring in SMT PCBA process and Wave Soldering Process. For the past 20 years, he has conducted more than 400 sessions of training/workshop for both on-site and public programs. More than three thousand participants have benefited from his training programs. These sessions were conducted mainly throughout Malaysia, in addition, he has also performed training overseas in various cities of Indonesia, China and Thailand. Apart from training, he provides consultations to companies, focusing on process troubleshooting and yield improvement. To further serving the SMT industry, he assisted in setting up the SMTA Penang Chapter as the Founding Chairman, which is affiliated to the SMTA International US. Of late, he was one of the IPC Professional Course Instructors in APEX International for consecutive 3 years since 2015.


PDC2 - Flip Chip, WLCSP, and FOWLP Assembly and Reliability

Instructor: John Lau, Ph.D., ASM


The major trend in the electronic industry today is to make products such as smartphones, tablets, wearables, internet of things, etc. more personal by making them smarter, lighter, smaller, thinner, shorter, and faster, while at the same time making them more friendly, functional, powerful, reliable, robust, innovative, creative, and less expensive. As the trend towards miniature and compact products continues, the introduction of cool products that are more user-friendly and contain a wider variety of functions will provide growth in the market. Some of the key technologies that are helping to make these cool product design goals possible are flip chip, WLCSP (wafer-level chip scale package), and FOWLP (fan-out wafer-level packaging). Their PCB (printed circuit board) assembly and solder joint reliability will be presented and discussed in this lecture. Since wafer bumping is the mother of flip chip and WLCSP technologies, it will be briefly mentioned first.

John Lau, Ph.D., ASM About the Instructor:

With more than 37 years of R&D and manufacturing experience in semiconductor packaging, John has published more than 440 peer-reviewed papers, 30 issued and pending patents, and 18 textbooks on, e.g., Advanced MEMS Packaging (McGraw-Hill Book Company, 2010), Reliability of RoHS compliant 2D and 3D IC Interconnects (McGraw-Hill Book Company, 2011), TSV for 3D Integration, (McGraw-Hill Book Company, 2013), and 3D IC Integration and Packaging (McGraw-Hill Book Company, 2016). John is an elected ASME Fellow and has been an IEEE Fellow since 1994.

Questions? Contact SMTA Conference and Meeting Manager, or call +1-952-920-7682.

Cancellation Policy: Registration fees will be refunded (less a $75 processing fee) if written notice is postmarked two weeks prior to the event date. Cancellations received within two weeks prior to event date will not be refunded to cover costs incurred.