Wednesday, August 15th
John H. Lau, Ph.D., ASM Pacific Technology
Recent advances in (1) flip chip such as wafer bumping, package substrate, assembly, and underfill, (2) fan-in WLCSP (wafer-level chip scale package) such as relaxation layer and under-bump metallurgy (UBM)-free WLCSP, and (3) FOWLP (fan-out wafer-level packaging) such as chip-first with die face-down, chip-first with die face-up, and chip-last or redistribution layer (RDL)-first will be presented in this study. Emphasis is placed on the latest developments of these technologies in the past few years. Their future trends will also be discussed.
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