Calendar of Events
Ohio Valley Chapter: Solder Roundtable Technical Meeting - Southern Ohio +
Rhinegeist Brewery, Cincinnati, OH
Avoiding the Pitfalls of Voiding in PCB Assemblies
Brook Sandy-Smith, Indium Corporation
Bottom termination component use has increased very quickly throughout the last decade. Typical assemblies now have many of these components, often varying types of BTCs on one assembly. What is there to do when one or more starts to show increased variation within the same process? Many investigations have been conducted to find materials that offer the lowest voiding in large ground plane solder joints. In addition, there are many process modifications that have been proposed over the last decade to alleviate voiding in BTC components. These include but are not limited to: pad design, pad patterning, stencil design, via positioning, solid solder addition, and reflow profile optimization.
Furthermore, improved pad design strategies have been proven in the industry. IPC committees are updating the recommendations for design and implementation of BTCs including big changes to the IPC-7093. This presentation will discuss these changes and how these strategies can be used to minimize voiding and ensure robust BTC assemblies.
ADVANTAGES, BENEFITS AND DURABILITY OF STENCIL NANO-COATINGS
Tony Lentz, FCT Assembly, BlueRing Stencils
Nano-coatings have been introduced by various stencil manufacturers, with the promise of addressing some of the challenges of solder paste printing. Stated benefits of nano-coatings include: reduced underside cleaning, reduced bridging, improved solder paste release and improvements in yield. With several Nano technologies already on the market and more likely to be introduced, how can the performance be quantified? How robust are these coatings? How long do they last? How can an assembler approach the ROI of these coatings? What hidden benefits or negative impacts should be considered?
This presentation gives a rigorous method for evaluating the performance and economic benefits of solder paste stencil nano-coatings. Criterion such as underside cleaning, bridging, solder paste deposit geometry, post-print cleaning, and abrasion resistance, durability of the coatings were all considered. Transfer efficiencies were studied across aperture sizes ranging from 0.30 to 0.80 area ratios. Also investigated were the effects of nano-coatings on transfer efficiencies of a variety of solder pastes. This presentation also addresses durability of nano-coatings in relation to the number of print cycles and underside wipe cycles applied as well as materials used for the underside wipe process. Guidelines for maximizing the life of the nano-coatings are given.
Cleanliness Testing and Its Relationship to Flux Reliability
Jason Fullerton, Customer Technical Support Engineer, Alpha Assembly Solutions
Cleanliness testing of printed circuit board assemblies (PCBAs) is a practice that was originally developed in the 1970s to assess the effectiveness of post-soldering cleaning processes. As no-clean soldering technology was developed in the late 1980s and into the 1990s, the practice of testing the “cleanliness” of a PCBA has been performed in an attempt to determine the acceptability of assemblies that have not been exposed to a cleaning process. This practice continue to this day.
This presentation outlines the basic theory of Surface Insulation Resistance (SIR) testing as a means of quantifying the performance of fluxes used as no-clean soldering materials. Testing of solder pastes using Resistance of Solvent Extract (ROSE) methods is compared to SIR testing of those materials, and localized extraction cleanliness testing of liquid wave soldering fluxes is compared to SIR testing of those materials.
The divergence in the pass/fail results between the cleanliness tests and SIR results for the flux materials tested is explored. Information on the proposed changes to IPC/J-STD-001 as a result of this new understanding of the relationship between cleanliness testing and flux reliability is provided.
Lead-free Solder Paste Development for Ultra Fine-Pitch Printing and Reflow of 03015 and 0201 Metric Chip Components
Shantanu Joshi, Koki Solder America Inc.
Due to the widespread popularity in mobile devices such as wearable devices and smartphones, demand for miniaturized or micro surface mount components, such as 0201 metric chip, flip chip packages, and fine-pitch surface mount land patterns to accommodate them are increasing. Consequently, solder paste is required to be compatible with this high-density surface mount technology.
When printing paste for 0402 metric chip components, stencil apertures of approximately 0.2mm diameter are used whereas for 0201 metric chip components, stencil apertures of the dimension 0.1mm diameter are needed. This presents challenges for both good printability and solderability. Conventional solder paste technology seems to be lacking in coping up with these stringent requirements.
Precise printability and optimum solder reflow parameters were evaluated on ultra-fine pitch surface mount board pads using conventional solder paste and a newly developed solder paste to understand compatibility with 0201 and 03015 metric chip components.
A test vehicle was used with 0402, 03015 and 0201 metric chip components. Type 5 (10-25um) and Type 6 (5-20um) no-clean lead-free Sn3Ag0.5Cu solder pastes were evaluated with two different stencil thicknesses,50um and 80um. The area apertures ratios varied from 0.28 to 0.94. The measurements of paste volume after printing were recorded using production solder paste inspection equipment.
After printing reflow studies were conducted on assembled 03015R and 0201C metric chip components to understand reflow behavior. The solder paste development included flux improvement to increase stencil release rate of the solder paste through the stencil apertures for the challenging stencil area aperture ratios used. The newly engineered heat resistant flux chemistry in the solder paste helped to reduce solder graping during reflow even with the small paste deposits on the board. Continual solder paste print studies as well as print to pause studies were conducted with the developed solder paste on 0201 metric and 0.3mm pitch QFP board land pads to understand the use of the solder paste in production. The results of the work will be discussed in detail.
Pan Pacific Microelectronics Symposium 2018 +
Dallas Chapter: JTAG | 1149.1 boundary scan test and beyond +
100 S Central Expy #63, Richardson, TX 75080
Adam Ley, Chief Technologist - ASSET InterTech, Inc.
Even since the early days of “JTAG”, it was about more than just boundary scan test. And today’s 1149.1 is not your father’s “JTAG” … Our presentation will open with the basics of JTAG 1149.1 boundary scan, for those who need an introduction, and then go deeper to examine issues of integration, utilization and value in the sphere of assembly test. Finally, we’ll explore what’s beyond mere boundary scan as well as what’s new and next for JTAG.
Date: February 9, 2018 @ 11am
Location: Aboca’s Italian Grill, 100 S Central Expy #63, Richardson, TX 75080
Pricing (Includes Lunch):
- FREE for New Members since prior meeting
- $10 for Committee Members
- $20 Members, employees of Corporate member companies, 1st time guests, and students
- $25 non-members, students, & guests – same price
- Cash at the door or credit card on-line (see below)
- I'll be there - paying at the door (Click here)
- Members: I'll be there - paying now for 10% Early Bird Discount (Click here)
- Non-Members: I'll be there - paying now for 10% Early Bird Discount (Click here)
- 11:00am - Check in and Networking
- 11:30am - Lunch Begins
- 11:45am - Chapter Announcements
- 12:00am - Feature Presentation
- 1:00pm - Adjourn
Adam ensures that ASSET’s non-intrusive board test (NBT) methodologies comprise a best-in-class solution to meet the evolving need for improved coverage of board test in the face of ongoing erosion of physical access. Pursuant to ASSET’s strong support for standards, Adam is an active participant in IEEE 1149.1, having previously served terms as working group vice chair and as standard technical editor (for the 2001 revision), as well as in nearly all related standards, to include: 1149.4, 1149.5, 1149.6, 1149.7, 1149.8.1, 1149.10, 1500, 1532, 1581, iNEMI boundary-scan adoption, PICMG MicroTCA, and SJTAG (system JTAG). Adam’s experience prior to ASSET spanned over a decade at Texas Instruments, Sherman TX, where he had roles in application support for TI’s boundary-scan logic products and for test and characterization of new logic families. Adam earned the BSEE degree from Oklahoma State University, Stillwater OK, in 1986.
Upper Midwest (Minnesota, Iowa & Dakotas) Chapter: February 20th: SMTA Upper Midwest Chapter hosts +
Upper Mid-west Chapter is bringing in a speaker for the following topic:
Printing in the Third Dimension; Design, Materials, Equipment & Applications in Electronics
Speaker: Charles E. Bauer, Ph.D., Senior Managing Director of TechLead Corporation
Date: Tuesday, February 20th, 2018
Cost: $30 Members/ $40 Non-members (make checks payable to SMTA)
- 1:15 to 1:30 PM - Registration
- 1:30 to 1:35 PM – SMTA announcements
- 1:35 to 2:30 PM – Chuck’s Presentation
- 2:30 to 4:00 PM – CyberOptics Presentation/Tour
- Times subject to change so please arrive before 1:15 PM.
Address/Directions to CyberOptics:
5900 Golden Hills Dr.
Minneapolis, MN 55416
LINK TO DIRECTIONS
Printing in the Third Dimension;
Design, Materials, Equipment & Applications in Electronics
Excitement around 3D printing continues full speed ahead whether in electronics, consumer goods or industrial systems. Understanding the capabilities, limitations and most importantly the complexities of 3d printing remains challenging despite significant progress in both equipment and materials. While not a comprehensive tutorial on 3D printing, this presentation introduces the application of 3D printing in electronics prototyping and manufacturing including;
- Types of 3d printing
- Design tools for 3d printed products
- Materials selection (availability and alternatives)
- Equipment choices
- Process capabilities and constraints
Charles E. Bauer, Ph.D. – Bio:
Charles E. Bauer, Ph.D. serves as Senior Managing Director of TechLead Corporation, a technology management company specializing in the electronics packaging, interconnection and assembly industry, as well as Director of the University of Portland’s Global Executive Leadership MBA program. Dr. Bauer focuses in the areas of strategic technology planning, market analysis and business development, particularly in the international arena. Recent foci include an emphasis on medical device applications including sensors and imaging systems.
Combining applications experience in implantable, surgical and diagnostic medical devices with extensive background in design and manufacturing, Dr. Bauer presents a balanced perspective between technology and practical implementation for real world products. With more than 40 years’ experience spanning the range from complex interconnection technologies (printed circuit boards, hybrid and IC metallization and fabrication) through complex packaging (multichip modules, system in package, 3D packaging) and assembly (die attach, wire bonding, flip chip, etc.) as well as nano-technology applications in electronics manufacturing, his publications exceed 250 papers, articles and columns. He lectures throughout the world on technology, business and market topics as well as serving on several corporate boards and international corporate, government and educational institution advisory councils.
A Senior Member of IEEE, he remains active in the SMTA, JIEP, ASM and IMAPS Europe as well. Dr. Bauer served on the Boards of both the SMTA and IMAPS and as President of IMAPS in 2001-2002. Awards received include Tektronix Technical Innovation Award, Fellow of IMAPS, the International Leadership Award from the SMTA, Jesuit High School Hall of Fame, University of Portland Significant 75 Alumni and SMTA 25th Anniversary Luminary as founder of the Pan Pacific Microelectronics Symposium.
To RSVP, please click here, or copy and paste the following address into your web browser:
Oregon Chapter: LEAD TINNING REQUIREMENTS FOR THE 21ST CENTURY +
LEAD TINNING REQUIREMENTS FOR THE 21ST CENTURY
Presenter: Roger Cox, President, BS Chem, MS ME
The solderability of components in the process of manufacturing printed circuit assemblies is key to the longevity and reliability of the finished product. Hot solder lead tinning is the most dependable method to mitigate tin whiskers and prevent their growth when changing from a RoHS finish to a tin-lead finish for high-reliability parts; or when changing to a RoHS-compatible finish when a lead-free finish is required; and hot solder lead tinning is also used to remove oxidized or contaminated solder surfaces in the instance of legacy components.
Molten solder tinning is also used for prevention of gold embrittlement. Successful solder attachment of components to a circuit assembly relies largely on the solderability of surfaces to be joined, establishing the optimum thickness of intermetallics for a strong, yet compliant joint. Achieving this requires complimentary chemistries with the appropriate
temperatures and dwell times. Many factors necessary for a successful, repeatable and reliable process must be understood and controlled, and the end product finally tested to show that the end result meets or exceeds a customer’s requirements.
This presentation will examine the need for a two pot, molten solder lead tinning process, what it achieves, and how it is successfully implemented and proven from a solderability
proof perspective, including results obtained from XRF analysis, wetting balance measurements and ionic cleanliness testing, in conjunction and in compliance with IPC/EIA JSTD-002 and ANSI/GEIA STD-0006 standards.
Roger Cox, has worked for HP for 23 years, was Director of Engineering and Quality for KeyTronic EMS for 5 years. Now President of CTS (Component Tinning Services). CTS specialty is hot solder dip of components to improve solderability to circuit board assemblies. Roger has BS in Chemistry and a Masters in Mechanical Engineering