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How to Design for Testability (DFT) for Today's Boards and Systems

Presenter: Louis Y. Ungar
Company: A.T.E. Solutions
Date Published: 7/12/2016

Description: Overview:
Detailed review of the various guidelines covered in the SMTA/TMAG Testability Guidelines. Part 1 of the Webtorial will introduce attendees to the issues surrounding testing of electronic circuit boards and systems. It introduces testing concept and the mix of testers normally used. This includes the JTAG/IEEE-1149.1 boundary scan as well as built-in self test (BIST). With a combination of these technologies, the idea of non-intrusive board (and system) test is explored. The Webtorial takes the view that DFT is the best way to improve test performance and cost effectiveness. Towards that end Part 2 provides specific DFT guidelines. It concludes with exploring new standards and developments in DFT that will improve testing of boards and systems in the future.

Part 1 - Understanding Test, Test Strategies

  • What’s in today’s IC?
  • Today’s (and Tomorrow’s) Boards and Systems
  • Testing Philosophy and Economics
       - Conceptual Design and Failure Mode Effects Analysis    - Board/System Test Economics
  • Design for Testability: What, Why, How, Who and most importantly When?

    The Test Mix
  • Design Verification Tests
       o Functional Simulations
       - Signal Integrity
       - Margining and Robustness
  • Environmental Stress Screening, HALT, HASS, Burn-In
  • Qualification and Acceptance Testing
  • Automated Inspections
       - Optical Inspection (AOI)
       - X-Ray Inspection (AXI)
       - Thermal Characterization
  • Connectivity Testing
  • Manufacturing Defects Analysis (MDA)
  • In-Circuit Testing
       - Bed-of-Nails Access
       - Flying Probe Test
  • Boundary-Scan (JTAG/IEEE-1149.x)
  • Functional Board Testing
  • Built-In Self Test (BIST)
  • System Level Test and Diagnoses
  • Field Support Testing

    Strategies Towards "Non-Intrusive Board Test"
  • Traditional In-Circuit followed by Functional Board Test
  • Injecting Boundary Scan and BIST into the Traditional Approach
  • Testing to parallel design – a new paradigm

    Part 2 – Implementing Design for Testability

    Detailed review of the various guidelines covered in the SMTA/TMAG Testability Guidelines.

  • Probing and Fixturing Guidelines
  • Flying Probe Guidelines
  • Vectorless Testing Guidelines
  • AOI Inspectability Guidelines
  • X-Ray Inspection Guidelines
  • Electrical Design Guidelines
  • Boundary Scan Guidelines
  • Analog and Mixed Signal Guidelines
  • Built-In Self Test Guidelines
  • Diagnoses and Support Guidelines

    The Future of DFT
  • How DFT makes sense… and dollars:
  • IEEE 1687 and Hierarchical Test
  • System JTAG (SJTAG)
  • Design for eXcellence (DFX)
  • Let's learn from the IC world: DFT to Scan to Compression to BIST to BISR (Built-In Self Repair)

    Who Should Attend:
    DFT is a design discipline that benefits test engineering, manufacturing, logistics, field support and even Marketing. In addition to overall quality improvement and more reliable end products, a major benefit of DFT is earlier time to market, and that is a major concern of all managers. Anyone who can influence or be influenced by DFT will find this Webtorial beneficial.

    Instructor Bio
    Louis Y. Ungar enjoys a well-known reputation in the electronics testing profession. He has built, programmed, and selected Automatic Test Equipment (ATE) for a large number of clients both in the commercial and military community. Having introduced the first university course on Automatic Testing and Design for Testability at UCLA, he and his company have taught similar courses to thousands around the world in publicly held forums, at company facilities and online. He has served on international standards committees, such as the IEEE. He led the Surface Mount Technology Association (SMTA) Testability Committee to publish the SMTA Testability Guidelines in 2002 and helped in the project to revise it several times since. He has helped develop an economic modeling tool, called The Test Flow Simulator and a testability management tool, called The Testability Director.

  • Key Words: 

    Design for Testability, BIST, ICT, AOI, Probing, Fixturing

      Members: $200.00 (Log on to receive the member rate)
      Non-Members: $300.00

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