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Higher Density Packaging: Manufacturability & Reliability

Presenter: Cheryl Tulkoff
Company: DfR Solutions
Date Published: 4/15/2014

Description: For higher density packaging, one of the most common drivers for failure is inappropriate adoption of these new technologies. The path from consumer products with relatively high volume and short lifetime to high reliability products is not always clear. Obtaining relevant processing information can be difficult since information is often segmented by industry. And, the focus is always on the opportunities and not the associated risks. Some of the alphabet soup of higher density package names and descriptions you’ll see include TSVs (through silicon vias), Stacked Die packages, PoP (package on package), MEMS (Micro-electromechanical systems), SiP (system in or on a package) , SoC (system on a chip), 3D packaging, CSP (chip scale packaging), integrated passives and so on. Examples of the packages to be reviewed and discussed from both manufacturability and reliability perspectives during this webtorial are described below. This webtorial will help you wade through the rhetoric to the details important to your product.

Package on package was developed initially to meet more performance and functionality in smaller space like mobile devices where high density substrates and small single chip packages were not enough. The benefits of PoP packaging are well known.
They include:

  • Less board real estate
  • Better performance (shorter communication paths between the micro and memory)
  • Lower junction temperatures (at least compared to stacked die)
  • Greater control over the supply chain (opportunity to upgrade memory and multiple vendors)
  • Easier to debug and perform F/A (again, compared to stacked die or multi-chip module or system in package)
  • Ownership is clearly defined: Bottom package is the logic manufacturer, the top package is the memory manufacturer, and the two connections (at least for one-pass) are the OEM

    Companies in small volume, high reliability industries have to understand the limitations and challenges of PoP though in terms of both manufacturability and reliability.

    Through Silicon Vias (TSV) are the next generation technology for SiP (system in package) devices. They are similar to plated through holes in a PCB. TSV Promised advantages include thinner packages and a greater level of integration between active die. Rather than by cost reduction, TSV usage will be justified by increased performance through increase in inter-die I/O, increase in bandwidth, and decrease in interconnect length. TSV processes still being optimized and overall cost must be reduced for widespread adoption.

    There are several factors that influence the reliability of MEMS (Micro-electromechanical systems) devices. The types of materials used and the shape of the device affect the probability and type of failure.

    The three types of failure mechanisms that can be encountered are:

  • Packaging defects. Cracks in the package can allow moisture in which will contaminate the MEMS device.
  • Packaging interfering with the device. The gap between the package and the device could collapse, interfering with the function of the device.
  • Device defects. Finally, the device can have flaws that lead to residual stress build up, eventually causing bowing and shorting. Proactive hard work will minimize issues when integrating any higher density packaging into designs.

    Instructor Bio:
    Cheryl Tulkoff has over 22 years of experience in electronics manufacturing with an emphasis on failure analysis and reliability. She has worked throughout the electronics manufacturing life cycle beginning with semiconductor fabrication processes, into printed circuit board fabrication and assembly, through functional and reliability testing, and culminating in the analysis and evaluation of field returns. She has also managed no clean and RoHS-compliant conversion programs and has developed and managed comprehensive reliability programs.

    Cheryl earned her Bachelor of Mechanical Engineering degree from Georgia Tech. She is a published author, experienced public speaker and trainer and a Senior member of both ASQ and IEEE. She had held leadership positions in the IEEE Central Texas Chapter, IEEE WIE (Women In Engineering), and IEEE ASTR (Accelerated Stress Testing and Reliability) sections. She chaired the annual IEEE ASTR workshop for four years and is also an ASQ Certified Reliability Engineer.

  • Key Words: 

    Packaging, Reliability, High Density

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