Higher Density Packaging: Manufacturability & ReliabilityPresenter: Cheryl Tulkoff
Company: DfR Solutions
Date Published: 4/15/2014
Package on package was developed initially to meet more performance and functionality in smaller space like mobile devices where high density substrates and small single chip packages were not enough. The benefits of PoP packaging are well known.
Companies in small volume, high reliability industries have to understand the limitations and challenges of PoP though in terms of both manufacturability and reliability.
Through Silicon Vias (TSV) are the next generation technology for SiP (system in package) devices. They are similar to plated through holes in a PCB. TSV Promised advantages include thinner packages and a greater level of integration between active die. Rather than by cost reduction, TSV usage will be justified by increased performance through increase in inter-die I/O, increase in bandwidth, and decrease in interconnect length. TSV processes still being optimized and overall cost must be reduced for widespread adoption.
There are several factors that influence the reliability of MEMS (Micro-electromechanical systems) devices. The types of materials used and the shape of the device affect the probability and type of failure.
The three types of failure mechanisms that can be encountered are:
Cheryl Tulkoff has over 22 years of experience in electronics manufacturing with an emphasis on failure analysis and reliability. She has worked throughout the electronics manufacturing life cycle beginning with semiconductor fabrication processes, into printed circuit board fabrication and assembly, through functional and reliability testing, and culminating in the analysis and evaluation of field returns. She has also managed no clean and RoHS-compliant conversion programs and has developed and managed comprehensive reliability programs.
Cheryl earned her Bachelor of Mechanical Engineering degree from Georgia Tech. She is a published author, experienced public speaker and trainer and a Senior member of both ASQ and IEEE. She had held leadership positions in the IEEE Central Texas Chapter, IEEE WIE (Women In Engineering), and IEEE ASTR (Accelerated Stress Testing and Reliability) sections. She chaired the annual IEEE ASTR workshop for four years and is also an ASQ Certified Reliability Engineer.
Packaging, Reliability, High Density
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