International Wafer-Level Packaging Conference 2013 Proceedings

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Temporary Bonding Material Total Thickness Variation (TTV) A. Jacobs, M. Privett, G. Brand  Abstract
Some Trends In The Field Of Silicon Interposers A. Rouzaud, G. Simon, JP. Polizzi  Abstract
Advances In 300mm WLCSP Spheron™ Cu Platted RDL Technology For Higher Density And Lower Cost Packaging André Cardoso, Anthony Curtis  Abstract
An Investigation On The Effect Of Upstream Processes On The Quality Of Cu-Cu Bonding Interconnect Under Controlled Manufacturing Environment Anh Nguyen, Daniel Pascual, Eric Malocsay, Kevin Fealey, Paul Tariello, Peter Reilly  Abstract
Optical Technologies For TSV Inspection Arun A. Aiyer, Nikolai Maltsev, Jae Ryu  Abstract
Implementation Of A Fully Molded Fan-Out Packaging Technology B. Rogers, C. Scanlan, and T. Olson  Abstract
Cost Comparison Of Multi-Die Fan-Out Wafer Level Packaging And 2.5D Packaging With A Silicon Interposer Chet Palesko, Amy Palesko; and E. Jan Vardaman  Abstract
Thin Die Interconnect Process For 3DIC Utilizing Multiple Layers Of 50 Micron Thick Die On 300mm Wafers With A Tack And Collective Bonding Approach For Manufacturability Daniel Pascual, Colin McDonough, Anh Nguyen, Megha Rao, Robert Carroll, Douglas Coolbaugh, Joseph Piccirillo, Robert Geer  Abstract
MEMS Packaging: What Makes It So Special? Eric Mounier, PhD., Rozalia Beica  Abstract
Interconnect Structure For Room Temperature 3D-IC Stacking Employing Binary Alloying For High Temperature Stability Eric Schulte, Matthew Lueck, Alan Huffman, Chris Gregory, Keith Cooper, Dorota Temple  Abstract
Modeling The Imidization Kinetics Of A Low Temperature Cure Photosensitive Polyimide In Solid State Frank Windrich; Mikhail Malanin, Klaus-Jochen Eichhorn, Brigitte Voit  Abstract
Exploring Process Interaction Of No-Flow Underfill And Thermo-Compression Bonding In D2D Stacking G. Capuz, R. Daily, T. Wang, H. Struyf, R.A. Miller, K.J. Rebibis  Abstract
Quality In 3D Assembly – Is “Known Good Die” Good Enough? James Quinn, Barbara Loferer  Abstract
Vacuum-Assisted Wet Processing For Advanced 3D Devices Jennifer Rieker, Gim Chen and Ismail Kashkoush; Damien Michel and Patrick Daoust; and Irina Stateikina  Abstract
Minimizing Cost Of Calibration And Test (COCT) To Drive Cost Reduction Of MEMS John Rychcik, Barbara Loferer  Abstract
Spring Contact Probes In Wafer Level Test: Fundamentals And Advanced Concepts Jon Diller and Frank Zhou  Abstract
Examination Of Key Packaging Metrics Of A Hermetically Sealed MEMS Accelerometer Joshua Krabbe MSc., Nick Wakefield Ph.D., Serguei Roupassov MSc., Andy vanPopta Ph.D. Peter Hrudey Ph.D., Siamak Akhlaghi Ph.D.  Abstract
TSV Resist And Etch Residue Removal For 3DIC Kimberly Pollard, Richard Peters, Mike Phenis, Yuanmei Cao, Travis Acra, Don Pfettscher, Meng Guo  Abstract
Converging Front-End, Back-End And Flat Panel Display Manufacturing Technologies To Meet 2.5/3D And Fan-Out Packaging Requirements Klaus Ruhmer, Rajiv Roy, Philippe Cochet, Elvino Da Silveira  Abstract
Polyimede PCB Embedded With Two Dies In Stacked Configuration Koji Munakata, Nobuki Ueta, Masahiro Okamoto, Kumi Onodera, Kazuhisa Itoi, Satoshi Okude and Osamu Nakao; and Jon Aday and Theodore (Ted) G. Tessier  Abstract
30 Years Of Wafer-Level Packaging For Microsystems: From Automotive To Mobile Electronics And Beyond Leland “Chip” Spangler, Ph.D.  Abstract
High-Speed Removal Of Thick Negative Photoresist In Advanced Packaging Applications Mani Sobhian, Arthur Keigler, Daniel Goodman; Patrick Kearney; and M. David Webster  Abstract
Multiple Wafer MEMS WLP Michael Shillinger  Abstract
Wafer Level Packaging For Ultraminiature/Low-Cost MEMS Accelerometers Noureddine Hawat, Zhiwei Duan, Yang Zhao, Ph.D.  Abstract
Microbump Lithography For 3D Stacking Applications Patrick Jaenen, John Slabbekoorn, Andy Miller; Warren W. Flack, Manish Ranjan, Gareth Kenyon, Robert Hsieh, Ha-Ai Nguyen  Abstract
A Process Level Comparative Analysis Between D2W Local And Collective 3D Bonding R. Daily, G. Capuz, T. Wang, P. Bex, H. Struyf, K. Rebibis  Abstract
Inspection And Metrology Solutions For Copper Pillar High Volume Manufacturing Rajiv Roy  Abstract
Single Wafer Resist Removal For Wafer-Level Packaging With Improved Process Integration Richard Peters, Travis Acra, Yuanmei Cao, Kimberly Pollard, Don Pfettscher, Meng Guo  Abstract
Low Warpage And Improved 2.5/3DIC Process Capability With A Low Stress Polyimide Dielectric Robert L. Hubbard and Bong-Sub Lee  Abstract
Novel Cheap Solutions For 3D Integration On Wafers With Thin Interposers Semyon D. Savransky, Ph.D.  Abstract
Overcoming the Productivity Challenges in Wafer Level Packaging Shekar Krishnaswamy and David F. Hanny  Abstract
Study Of The Electroless Plating Process For Special Materials Or Small Pads For UBM Formation Shigeo Hashimoto, Yukinori Oda, Shinji Ishimaru, Hiromu Inagawa; and Don Gudeczauskas  Abstract
Automating The Design And Layout Of Wafer Level Masks Steve DiBartolomeo  Abstract
Metal Inter-Diffusion And Eutectic Wafer Bonding Processes For Advanced Mems Packaging Sumant Sood, Robert Hergert; and Oliver Treichel  Abstract
Micro Ball Bumping Packaging For Wafer Level & 3-D Solder Sphere Transfer And Solder Jetting Thomas Oppert, Thorsten Teutsch, Ghassem Azdasht, Elke Zakel, Richard McKee  Abstract
Recent Results Using MET-Via TSV Interposer Technology As TMV Element in Wafer Level Through Mold Via Packaging of CMOS Biosensors Thorbjörn Ebefors, PhD, Jessica Fredlund, Erik Jung and Tanja Braun, PhD  Abstract
Choosing Lithography Equipment To Minimize The Cost Of Wafer Level Packaging Tim McCrone, Robert Hergert; and Ralph Zoberbier  Abstract
2.5D And 3D Packaging Platform For Next Generation RF And Digital Modules Using Through Glass Vias (TGV) Technology Tim Mobley and Sergio Cardona  Abstract
Reliable Interconnection With Electroplated Cu Pillars And SnAg Solder Caps Yi Qin, Jui-Ching Lin, Julia Woertink, Jonathan Prange, Pedro Lopez Montesinos, Inho Lee, Yil- Hak Lee, Masaaki Imanari, Erik Reddington, Mark Lefebvre, Jianwei Dong, Wataru Tachikawa, Jeffrey Calvert  Abstract
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