International Wafer-Level Packaging Conference 2012 Proceedings

While abstracts in the Knowledge Base are accessible to all visitors, the full articles (PDF format) are FREE FOR SMTA MEMBERS to download.

Members download articles for free:

Not a member yet?

What else do you get when you join SMTA? Read about all of the benefits that go along with membership.

< Back to Conferences List

Wafer Spray Coating For Pre-Applied Underfill Akira Morita and James Klocke  Abstract
Adaptive Patterning For Panelized Packaging C. Scanlan, B. Rogers, T. Olson, C. Bishop, J. Kellar, and B.Y. Jung  Abstract
Deposition Processes for Competitive Through Silicon Via Interposer for 3D Cyprian Uzoh, Rezwana Sharna, Pejman Monajemi, Michael Newman, Charles Woychik and Terrence Caskey  Abstract
Room Temperature Debonding - An Enabling Technology for TSV and 3D Integration Garrett Oakes, Thorsten Matthias, Eric Pabo, Jürgen Burggraf, Daniel Burgstaller, Markus Wimplinger, and Paul Lindner  Abstract
Sealing Dispensing for MEMS Wafer Capping Heakyoung Park  Abstract
Low Stress Thick Film Photopatternable Thick Film Silicones for Large Die Wafer Level Applications Herman Meynen, Ranjith John, Ken Weidner, Craig Yeakle, Mike Bourbina, Arianne Tan, Brian Russell, and James Rosson  Abstract
Marked Reliability Increase of Plastic-Cored Solder Ball for Large Size Wafer-Level CSP Hiroya Ishida and Kiyoto Matsushita  Abstract
Developments of Fan-Out Wafer Level Packaging Technology for System-In-Package on Wafer-Level (WLSIP) J. Campos; E. O'Toole; V. Henriques; A. Martins; A. Leão; A. Cardoso; A. Janeiro  Abstract
Embedded Barrel Spring Probe - Solution For WLCSP Testing Jiachun Zhou (Frank) and Jon Diller  Abstract
Yield and Strength of Metal Wafer-Level MEMS Device Sealing Using Al, Au, or Ti K. Schjølberg-Henriksen, PhD; E. Poppe, A.S. Moen, and E. Fasting  Abstract
Pad Lift Failure Mode Investigation for Wafer Level Package Laurent Gay, Sebastien Gallois-Garreignot, Francois Guyader, Romain Brouillac, Pauline Boissiere  Abstract
Wafer-Level Testing Challenge For Flip Chip and Wafer-Level Packages Lim Kok Hwa and Andy Chee  Abstract
Bonding and Contacting of Vertically Integrated 3-D Microscanners M. Wiemer, J. Frömel, C. Jia, S. Bargiel, M. Baranski, N. Passilly, and C. Gorecki  Abstract
Package Modeling of MEMS Devices Manickam Thavarajah & John Bloomsburgh  Abstract
MEMS Integration Issues Mary Ann Maher  Abstract
Co-Design Strategies for MEMS Packaging Mary Ann Maher and Sebastien Cases  Abstract
Heterogeneous Packaging for MEMS Matt Apanius  Abstract
MEMS Hermeticity and Reliablility Testing Today Michael Shillinger  Abstract
Silicone and Cleaning Solvent Compatibility Michelle Velderrain and Danielle Peak  Abstract
A Study of a Development Lithography Processes for 3Di Plating Applications Patrick Kearney, Kirsten Ruck, Kathleen Nafus, Tetsushi Miyamoto, Patrick Jaenen, and Andrew Miller  Abstract
Optical Profilometry of Substrate Bow Reduction Using Temporary Adhesives Paul Flynn and John Moore  Abstract
Understanding the Stacked Dies Interface Temperature and Its Influence During the 3D Ic Thermocompression Stacking Process R. Daily, G. Capuz, P. Bex, A. Miller  Abstract
Single Sided Wet Etching For Texturing, Thinning and Packaging Applications Ricardo I. Fuentes, Ph.D.  Abstract
Evaluating Methods of Shipping Thin Silicon Wafers for 3D Stacked Applications Richard A. Allen, Urmi Ray, Vidhya Ramachandran, Iqbal Ali, David Read, Andreas Fehkührer and Jürgen Burggraf  Abstract
A New Single Wafer Cleaning Technology For Advanced Packaging Applications Richard Peters, Travis Acra, Spencer Hochstetler, Kimberly Pollard, Keith Cox, Don Pfettscher, Thorsten Matthias, Thomas Glinsner, and Martin Schmidbauer  Abstract
3D TSV Micro Cu Pillar Chip-To-Substrate/Chip Assembly/Packaging Technology Seung Wook Yoon, K. T. Kang, W. K. Choi, H. T. Lee, Andy C. B. Yong and Pandi C. Marimuthu  Abstract
Innovative 2.5D Solution: Extended / Flip Chip eWLB (Embedded Wafer Level Ball Grid Array) Technology Seung Wook Yoon, Yaojian Lin and Pandi C. Marimuthu  Abstract
Characterization of eWLB PoP Structures Tom Strothmann  Abstract
Reliability of TSV and Wafer-Level Bonding for a 3D Integrable SOI Based MEMS Application Torleif André Tollefsen, Maaike M. Visser Taklo, Thor Bakke, Nicolas Lietaer, Per Dalsjø, and Jakob Gakkestad  Abstract
TSV Process Variations for 2.5D and 3D Semiconductor Packaging Vern Solberg  Abstract
3D Packaging - Synthetic Quartz Substrate and Interposers for High Frequency Applications Vern Stygar, Tim Mobley  Abstract
Verification of Back-To-Front Side Alignment for Advanced Packaging Warren W. Flack, Manish Ranjan, Gareth Kenyon, Robert Hsieh, John Slabbekoorn, and Andy Miller  Abstract
SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344 USA

Phone +1 952.920.7682
Fax +1 952.926.1819