MEMBERS LOGIN
International Wafer-Level Packaging Conference 2011 Proceedings
While abstracts in the Knowledge Base are accessible to all visitors, the full articles (PDF format) are FREE FOR SMTA MEMBERS to download.
Members download articles for free:
Not a member yet?
What else do you get when you join SMTA? Read about all of the benefits that go along with membership.
| TITLE | AUTHOR | |
| Disruptive Wafer-Level Package-On-Package Technology | A.G. Holland. | Abstract |
| Cost Comparison Of Fine Pitch Chip Scale Packaging Technologies | Alan Palesko and Chet Palesko | Abstract |
| Effects Of Current Density And Pulse Frequency On Electroplated Copper Solder Joint Reliability | Darren Moore PhD, JD Sumega MSc. | Abstract |
| Product, Adhesive, And Carrier Wafer Thickness Measurement | David Marx, David Grant, and Russ Dudley | Abstract |
| Board Level Reliability Of Wafer Level CSPs For Telecommunication System Applications | Ding Li, Xiangyong Qing, Lei Feng, Zhenkai Qin, Yuming Ye, and Weifeng Liu, Ph.D. | Abstract |
| Evolution, Challenge, And Outlook Of TSV, 3D IC Integration And 3D Silicon Integration | John H. Lau | Abstract |
| New Applicationsfor Fan-Out Wafer Level Packaging Technology | José Campos | Abstract |
| Intermetallic Slid Bonding (Cu-Sn And Au-Sn) For Wafer Level Encapsulation | K. Wang, K.E. Aasmundtveit, and N. Hoivik, Ph.D. | Abstract |
| Laminate Based Fan-Out Embedded Die Packaging Using Polyimide Multilayer Wiring Boards | Kazuhisa Itoi, Masahiro Okamoto, Yoshinori Sano, Nobuki Ueta, Satoshi Okude, and Osamu Nakao, Theodore (Ted) G. Tessier, Senthil Sivaswamy, and Gene Stout | Abstract |
| Process And Equipment Enhancements For C2W Bonding In A 3D Integration Scheme | Keith A. Cooper, Michael D. Stead, Daniel Pascual, and Eric F. Schulte, Gilbert Lecarpentier, and Jean-Stephane Mottet | Abstract |
| Resist Removal Technology For Next Generation 3D Packaging Solutions | Kimberly D. Pollard, Jim Cooper, Allison Rector, Jeff Griffin, Nicole Skaggs, Craig Atkinson, Nichelle Wheeler, and Mike Phenis | Abstract |
| Identifying The Mechanism Of Stress-Assisted Void Growth In Through Silicon Via (TSV) By X-Ray Microscopy And Finite Element Modeling | LayWai Kong, James R. Lloyd, Ph.D., Michael Liehr, Ph.D., Alain C. Diebold, Ph.D., Ehrenfried Zschech, Ph.D., and Andrew C. Rudack | Abstract |
| Wafer Level Vacuum Encapsulation For An Uncooled Microbolometer Array | Martin Bring, Ph.D., Adriana Lapadatu, Ph.D., Tor Ivar Simonsen, Gjermund Kittilsland, and Lic.Eng. | Abstract |
| High Density TSV Chip Stacking Fabless Infrastructure Status | Matt Nowak | Abstract |
| Wafer-Level Packaged MEMS Switch With TSV | Nicolas Lietaer, Thor Bakke, Anand Summanwar, Per Dalsjø, Jakob Gakkestad, and Frank Niklaus | Abstract |
| Design Concept And Processing Solution For Molded Via BGA | Paul T. Lin and Michael B. McShane | Abstract |
| System-In-Package Solutions With IMB® Substrates | Risto Tuominen, M.Sc., Tuomas Waris, Tanja Karila, Janne Mettovaara, Markus Eklund, Sara Hardy-Baloun | Abstract |
| System-In-Package Opportunities With The Redistributed Chip Package (RCP) | Scott Hayes, Navjot Chhabra, Trung Duong, Zhiwei (Tony) Gong, Doug Mitchell, and Jason Wright | Abstract |
| Ewlb (Embedded Wafer Level Bga) Technology: Dawn Of A New Age Of Thin And 3D Package Technology | Seung Wook Yoon, Yaojian Lin, Chow Seng Guan, and Pandi C. Marimuthu | Abstract |
| Potential Of Large Area Mold Embedded Packages With PCB Based Redistribution | T. Braun, K.-F. Becker, L. Böttcher, A. Ostmann, E. Jung, S. Voges, T. Thomas, R. Kahle, V. Bader, J. Bauer, R. Aschenbrenner, M. Schneider-Ramelow, and K.-D. Lang | Abstract |
| Lithography Challenges For Leading Edge 3D Packaging Applications | Warren W. Flack, Manish Ranjan, Gareth Kenyon, Robert Hsieh, John Slabbekoorn, and Andy Miller | Abstract |
| Packaging Nanoporous Energetic Silicon For On-Chip Mems Applications | Wayne A. Churaman, Collin R. Becker, Christopher J. Morris, Luke J. Currano, and Chia-Chen Wu, and Michael J. Sailor | Abstract |
| Design For Board Level Reliability Improvement In EWLB (Embedded Wafer Level BGA) Packages | Won Kyoung Choi, Yaojian Lin, Chen Kang, Seng Guan Chow, Seung Wook Yoon, and Pandi Chelvam Marimuthu | Abstract |
| Development Of Next Generation eWLB (Embedded Wafer Level BGA) Technology | Yonggang Jin, Jerome Teysseyrex, Xavier Baraton, Seung Wook Yoon, Yaojian Lin, and Pandi Chelvam Marimuthu | Abstract |