International Wafer-Level Packaging Conference 2018 Proceedings

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TITLE AUTHOR
Low-Density Fan-Out SiP for Wearables and IoT with Heterogeneous Integration A. Martins, M. Pinheiro, A. F. Ferreira, R. Almeida, F. Matos, J. Oliveira, Eoin O'Toole, H. M. Santos†, M. C. Monteiro, H. Gamboa, R. P. Silva  Abstract
High Density and High Bandwidth Chip-To-Chip Connections with 20µm Pitch Flip-Chip on Fan-Out Wafer Level Package A. Podpod, D. Velenis, A. Phommahaxay, P. Bex, F. Fodor, EJ. Marinissen, K. Rebibis, A. Miller, G. Beyer and E. Beyne  Abstract
An Innovative Application of Fan-Out Packaging for Test & Measurement-Grade Products Barrett Poe  Abstract
Advancing Advanced Process Control in Backend Factories Ben Williams, Todd Nowalk, Chris Reeves  Abstract
Design Trends and Challenges of Advanced Wafer-Level Manufacturing and Fanout Bill Acito  Abstract
The Road to Wafer-On-Wafer (Wow) High Volume Manufacturing (HVM)-Advanced Sensing in Wafer Handling Boris Kesil  Abstract
Fan-Out Wafer Processing in the High Density Packaging Era David Butler, Chris Jones, Steve Burgess, Tony Wilby and Paul Densley  Abstract
Advanced EWLB (Embedded Wafer Level Ball Grid Array) Solutions for mmWave Applications Dian Wang, Fazhi An and Seung Wook Yoon  Abstract
Antenna Integration Technologies for 5G Car-Application Fabian Hopsch, Andy Heinig  Abstract
Development of Low Temperature Direct Bond Interconnect Technology for Die-To-Wafer and Die-To-Die Applications—Stacking, Yield Improvement, Reliability Assessment Guilian Gao, Laura Mirkarimi, Thomas Workman, Gabe Guevara, Jeremy Theil, Cyprian Uzoh, Gill Fountain, Bongsub Lee, Pawel Mrozek, Michael Huynh, Rajesh Katkar  Abstract
Fine RDL Formation Using Alternative Patterning Solution for Advanced Packaging Habib Hichri; Markus Arendt; Richard Hollman; Ognian Dimov; Sanjay Malik  Abstract
Comparative Study of 3D Package Configurations in Power Delivery and Thermal Perspective Heeseok Lee, Yunhyeok Im, and Youngmin Shin  Abstract
Fabrication of Redistribution Structure Using Highly Reliable Photosensitive Polyimide for Fan Out Panel Level Packages Hitoshi Araki, Yu Shoji, Yuki Masuda, Keika Hashimoto, Kazuyuki Matsumura, Yutaro Koyama, and Masao Tomikawa  Abstract
Study of Fine Pitch RDL First FO-PLP/WLP Hitoshi Onozeki, Hiromichi Aoki, Kohei Mizuno, Mitsuki Nakata, Naoya Suzuki, Tsuyoshi Ogawa, Toshihisa Nonaka  Abstract
Chip Board Interaction Analysis of 22-nm Fully Depeleted Silicon on Insulator (FD-SOI) Technology in Wafer Level Packaging (WLP) Jae Kyu Cho, Jens Paul, Simone Capecchi, Dirk Breuer, and Frank Kuechenmeister, Doug Scott, JongJin Choi, and Wonjoon Kang  Abstract
Enabling Reliability of 3D TSV Advanced Packages with Non-Conductive, Pre-Applied Underfill Film Materials Jie Bai, Kail Shim, James Jang, Kevin Lindsey, Haiying Li, Qizhuo Zhuo, Rose Guino, and Ramachandran K. Trichur  Abstract
Redistribution-Layers (RDLS) for Fan-Out Panel-Level Packaging John H Lau  Abstract
Wave Front Phase Imaging of Wafer Warpage Juan Trujillo, Jose Manuel Ramos Rodrigues, Jan Gaudestad  Abstract
Large Area Encapsulation: Solid Type Epoxy Molding Compound Junghwa Kim, Ph. D., JungSeob Kim, Ki-Hyeok Kwon, Ph. D., Yang-Seung Yong, Jae-Hyun Kim, Dong-Hwan Lee, Ph. D., Sang-Kyun Kim, Ph. D., Deokhoon Park, Jiyoung Song  Abstract
Multiscale Models for Electroplating of Through Silicon Vias K. H. Khoo, Lai MingRui, H. Ramanarayan, J. Hongmei, S. Wu, C. A. Joshi, K. R. Mangipudi, J. J. Cheng, S. S. Quek, D. T. Wu, N. Sridhar, M. S. Bharathi  Abstract
Fabrication of a High Precision Magnetic Position Sensor Based on a Through Silicon Via First Approach Kai Zoschke, Hermann Oppermann, Johannes Paul, Heiko Knoll, Franz-Josef Braun, Monika Saumer, Martin Theis, Peter Frank, Andreas Lenkl, Fabian Klose  Abstract
Advanced Packaging Metrology and Lithography That Overcomes FOWLP/FOPLP Die Placement Error Keith Best and Mike Marshall  Abstract
A Practical Guide for First-Time FOWLP Design Success Kevin Rinebold, John Ferguson, Keith Felton  Abstract
Significant Advancement in Laser Ablative Release Layer Material Design Enabling Low-Energy and Low-Residue Debond Luke Prenger, Qi Wu, Arthur Southard, Debbie Blumenshine, Rama Puligadda  Abstract
Optical Run-Out Correction for Improved Lithography Overlay Accuracy for FOWLP Applications Markus Arendt, Matthew Gingerella, Habib Hichri  Abstract
Degas Module Thermal Architecture, Variable Wafer Delays, and Throughput, Productivity, and Consistency in Fan-Out Packaging Barrier/Seed Layer PVD Paul Werbaneth, Billy Runstadler, Sam North, Vladimir Kudriavtsev, Sriram Krishnaswami, Luy Danh, Terry Bluck, and Camron Blonigan  Abstract
Temporary Bonding and the Challenge of Cleaning Post-Debond Phillip Tyler, Kenji Nulman, Laura Mauer, Michelle Fowler and Seth Molenhour  Abstract
Wafer-Level Fan-Out for High-Performance, Low-Cost Packaging of Monolithic RF MEMS/CMOS Rameen Hadizadeh, Anssi Laitinen and David Molinero, Ph.D., Nelson Pereira and Márcio Pinheiro  Abstract
Failure Relief in WLP and PLP Polymer Layers Robert L. Hubbard, Ph.D.  Abstract
Exposed Die Fan-Out Wafer Level Packaging by Transfer Molding S.H.M. Kersjes, J.L.J. Zijl, N. de Jong, H. Wensink  Abstract
Thermal Debonding and Warpage Adjust of FOWLP - A Crucial Step in the Evolution of Advanced Packaging? Sophia Oldeide, Regine Beckmann, Laurent Giai-Miniet, Klemens Reitinger  Abstract
Reducing the Cost of Applying Ultra-Thin, Package Level EMI Shield Coatings Stuart Erickson  Abstract
Recent Developments in Panel Level Packaging Tanja Braun, Mathilde Billaud, Hannes Zedel, Lutz Stobbe, Karl-Friedrich Becker, Ole Hoelck, Markus Wöhrmann, Lars Boettcher, Michael Töpper, R. Aschenbrenner, Steve Voges, Klaus-Dieter Lang, Martin Schneider-Ramelow  Abstract
Heterogeneous Integration by Collective Die-To-Wafer Bonding Thomas Uhrmann, Jürgen Burggraf, Martin Eibelhuber  Abstract
Board Level Reliability Study of Next Generation Large Die Wafer Level Chip Scale Package Structures Timo Henttonen, Paul Mescher, Doug Scott, Han Park, YongJae Ko and Kevin Engel  Abstract
Improve Control Amidst Die Shrink, 3D Package Complication Woo Young Han, Mike Marshall, Matt Wilson  Abstract
High Speed 3D Inspection of Advanced Package Interconnect Uniformity Zonghu He Ph.D. and John Schaefer B.E.E.  Abstract
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