International Wafer-Level Packaging Conference 2017 Proceedings

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TITLE AUTHOR
Advanced Packaging Inspection Solutions for Fan Out Panel Level Processing Benjamin Meihack, Mike Marshall  Abstract
Hybrid Copper Dielectric Direct Bonding of 200 mm CMOS Wafers with Five Metal Levels: Morphologic, Electrical and Reliability Characterization Celso Cavaco, Lan Peng, Stefano Guerrieri and Haris Osman  Abstract
Wafer Thinning In-Line Inspection Process Control Solution for High-Volume Manufacturing Cleonisse Serrecchia  Abstract
Die-Level Traceability Using Adaptive Patterning Craig Bishop, Jiyang Zhou, Edgar Ege  Abstract
Low Temperature Curable PI/PBO for Wafer Level Packaging Daisaku Matsukawa, Nobuyuki Saito, Satoshi Abe, Atsutaro Yoshizawa, Noriyuki Yamazaki, Tetsuya Enomoto, Takeharu Motobe , Yuhei Okada, Toshihisa Nonaka  Abstract
Optical Inspection for Heterogeneous Integration of Electronic Systems Dr. Shye Shapira  Abstract
Fan Out Package Technology Based SIP for Advanced RF and High Performance Applications Gaurav Sharma, BooYang Jung and Marcel Wieland  Abstract
Have You Designed for Manufacturing Test? Gerard John  Abstract
Development of Hybrid Bond Interconnect Technology for Die-To-Wafer and Die-To-Die Applications Guilian Gao, Gill Fountain, Cyprian Uzoh, Bongsub Lee, Laura Mirkarimi, and Liang Wang  Abstract
Electrical and Reliability of Ultra-Fine Line Multi-Redistribution Layers Enabled By an Innovative Excimer Laser Dual Damascene Process for Wafer-Level Packaging Habib Hichri, Robert Gernhardt, Markus Woehrmann, Markus Arendt, Klaus-Dieter Lang  Abstract
Transfer of Wafer Level Packaging to Panel Format Henning Hübner, Dr. Christian Ohde, Ralph Zoberbier, James Welsh  Abstract
Novel Low-Temperature Curable Positive-Tone Photosensitive Dielectric Materials with High Elongation for Panel Level Package Hitoshi Araki, Ph.D., Yu Shoji, Ph.D., Yuki Masuda, Keika Hashimoto, Kimio Isobe, Yutaro Koyama, Ryoji Okuda and Masao Tomikawa, Ph.D.  Abstract
Wafer Level Package Material and Process Hitoshi Onozeki, Kouji Hamaguchi, Keisuke Nishido, Naoya Suzuki, Toshihisa Nonaka  Abstract
Fan-Out Wafer Level EWLB Technology as an Advanced System-In-Package Solution Jacinta Aman Lim, Vinayak Pandey, Aung Kyaw Oo, Andy Yong  Abstract
Contractor Materials & Impacts on Tip Wear & Life for WLCSP Testing Jiachun Zhou (Frank), Ph.D., Hui Liu  Abstract
Challenges of ECD Panel Fan-Out in High Volume and Potential Solutions Jon Hander, Demetrius Papapanayiotou, Robert Moon, Arthur Keigler, Michelle Schulberg, Mani Sobhian, Bryce Chen, Tyler Barbera, Cristina Chu  Abstract
Package Assembly Design Kits - The Technology Bridge Between Chip Design and Wafer-Level Manufacturing and Assembly Jonathan Micksch  Abstract
Fan-Out WLP Technology as Sensor Packaging Solution Jong Heon KIM, Yun-Mook Park, Yong Tae KWON, JK Lee, Seo Hee LEE  Abstract
Application of Infrared Inspection to Thermo-Compression Bonding and Die Placement Processes Justin Brubaker and Tom Strothmann  Abstract
Enabling Fan-Out Wafer-Level Package (FOWLP) Through Innovative Lithography and Electrodeposition Technology Justin Oberst, Bryan Buckalew, Thomas Ponnuswamy, Manish Ranjan, Robert Hsieh, Ha-Ai Nguyen, Warren W. Flack  Abstract
Fine Pitch Plating Resist for High Density FO-WLP Kenji Okamoto, Tomoyuki Matsumoto, Makoto Katsurayama, Hirokazu Ito, Hisanori Akimaru, Hirokazu Sakakibara, Koichi Hasegawa  Abstract
Photo-Sensitive Insulation Film for Encapsulation and Embedding Kiichi Fukuhara, Ph.D., Shigeo Tanaka, Toshizumi Yoshino, MBA., Kazuyuki Mitsukura, Tomonori Minegishi, Ph.D. and Kazuhiko Kurafuchi  Abstract
Connectivity Management of Vertically Integrated Multi-Substrate Heterogeneous Packages Magesh Govindarajan, Keith Felton, John Ferguson, Kevin Rinebold  Abstract
Comparison of Different Communication Interfaces between Chips Assembled onto Silicon Interposer Muhammad Waqas Chaudhary and Andy Heinig  Abstract
Rc Management for Next Generation PVD UBM/RDL Metallization Schemes Nick Knight, Steve Burgess, Chris Jones, Anthony Barker, Tony Wilby, Paul Densley  Abstract
Fine Pitch Cu Pillar Assembly Challenges for Advanced Flip Chip Package Nokibul Islam, Ming-Che Hsieh, Kang KeonTaek, Vinayak Pandey  Abstract
Toward a Flip-Chip Bonder Dedicated to Direct Bonding for Production Environment P. Metzger, Ph.D., N. Raynaud, A. Jouve, N. Bresson, L. Sanchez, F. Fournel, S. Cheramy  Abstract
3D Integration for Mobile Security – A Secure Smart Card Application René Puschmann, Michael Ziesmann, Alexander Schwarz, M. Jürgen Wolf, K. Dieter Lang  Abstract
Temporary Bonding for High Temperature Processing of Thin Glass Robert A. Bellman, Prantik Mazumder, Robert G. Manley, Kaveh Adib, Shiwen Liu, and Leena Sahoo  Abstract
Challenges of Ball-Attach Process Using Flux for Fan-Out Wafer/Panel Level (FOWLP/PLP) Packaging Sze-Pei Lim, Dr. Yan Liu, John H Lau, and Li Ming  Abstract
Fan-Out Wafer and Panel Level Technology for Advanced LED Packaging T. Braun, R. Kahle, S. Voges, S. Raatz, P. Graap, O. Hölck, J. Bauer, K.-F. Becker, R. Aschenbrenner, S. Voges, M. Dreissigacker, K.-D. Lang, J. Moosburger, F. Singer, L. Höppel  Abstract
Micro Thin-Film Li-Ion Battery Stacking Technology by Backside Via Last TSV for IoT Devise Takahide Murayama, Akiyoshi Suzuki, Yasuhiro Morikawa  Abstract
Process and Productivity Results from a Carrier-Based Linear Transport PVD System for RDL Seed Layer Deposition in Fan-Out Packaging Applications Terry Bluck, Chun-Chung Chen, Daniel Gallagher, Vladimir Kudriavstev, Lisa Mandrell, Billy Runstadler, Chris Smith, Paul Werbaneth  Abstract
The Benefits Oo Source Die Input Flexibility in a TCB Process Tom Strothmann  Abstract
New Cad Tools Feature for Virtual Prototyping Tom Whipple and Yoko Fujita  Abstract
Dual Side Chip Cooling Realized by Microfluidic Interposer Processing on 300mm Wafer Diameter Wolfram Steller, Frank Windrich, Philipp Heilfort, Jessica Kleff, Raúl Mroßko, Jürgen Keller, Thomas Brunschwiler, Gerd Schlottig, Hermann Oppermann, Jürgen M. Wolf, and Klaus-Dieter Lang  Abstract
A Novel Dual-Layer Bonding Platform as a Technical Enabler for Wafer Level Packaging Application Xiao Liu*, Qi Wu, Jayson Cooper, Kuo Han, Dongshun Bai, Matt Koch, Rama Puligadda, Tony Flaim  Abstract
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