International Wafer-Level Packaging Conference 2015 Proceedings

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An Analysis of Key Cost and Yield Drivers for Fan-Out Wafer Level Packaging Amy Palesko  Abstract
Massively Parallel 3D Inspection and Metrology of µfeatures in 3D Packaging Arun A. Aiyer, Tianheng Wang  Abstract
Chips Face-Up Panelization Approach for Fan-Out Packaging B. Rogers, D. Sanchez, C. Bishop, C. Sandstrom, C. Scanlan and T. Olson  Abstract
Dual Chip Wafer Level CSP with Sintering Paste LGA Catherine Shearer, Ken Holcomb, Michael Matthews, Maria Spiteri and Ivan Ellul  Abstract
Approaches and Challenges for 3D IC Packaging Charles G. Woychik, Sangil Lee, Guilian Gao, Liang Wang, Hong Shen, Akash Agrawal, Mohamed Elassar, Scott McGrath and Sitaram Arkalgud  Abstract
Assemblies Containing Copper Pillar Structures Processed Using One Step Chip Attach Materials (OSCA) and Conventional Mass Reflow Processing Daniel Duffy Ph.D., Hemal Bhavsar, Lin Xin, Jean Liu, Bruno Tolla Ph.D.  Abstract
3D technology, TSV, via reveal, end-point detection, viamiddle, via-last, wafer thinning Dave Thomas, Janet Hopkins, Huma Ashraf, Jash Patel, Oliver Ansell, Anne Jourdain, Joeri De Vos, Andy Miller and Eric Beyne  Abstract
The X-Ray Metrology of TSVs David Bernard, John Tingay, Philip Moyse & Will Heeley  Abstract
DSC300 GEN2 Platform - Projection Lithography Performance with Advantages of Full-Field Exposure Technology Habib Hichri, Ralph Zoberbier, Jelena Pesic, Eric Nguyen  Abstract
Temporary Wafer Carrier Solutions for Thin FOWLP and eWLB-based PoP Jose Campos, André Cardoso, Mariana Pires, Eoin O'Toole, Raquel Pinto, Steffen Kröhnert, Emilie Jolivet, Thomas Uhrmann, Elizabeth Brandl, Jürgen Burggraf, Harald Wiesbauer, Julian Bravin, Markus Wimplinger and Paul Lindner  Abstract
Integration Through Wafer-Level Packaging Approach Kai Liu, Bernard Adams, and SeungWook Yoon  Abstract
Metrology Considerations for Through Silicon Via Manufacturing Ke Xiao, Sanjeev Singh, Holly Edmundson, John Allgair, Timothy Johnson, Daniel Smith, Yudesh Ramnath  Abstract
Advanced Lithography and Electroplating Approach to Form High-Aspect Ratio Copper Pillars Keith Best, Roger McCleary, Richard Hollman and Phillip Holmes  Abstract
3D Wafer Level Packaging by Using Cu-Through Silicon Vias for Thin Mems Accelerometer Packages L. Hofmann, I. Schubert, D. Wünsch, R. Ecke, K. Vogel, K. Gottfried, D. Reuter, M. Rennau, S.E. Schulz, T. Geßner  Abstract
A Study of Microbump Metrology and Defectivity at 20 Micron Pitch and Below for 3D TSV Stacking Leander Haensel, Maarten Liebens, Tom Vandeweyer, Andy Miller, Eric Beyne, Markus Wiesiollek, Heiko Eisenbach, Marc Filzen, Youxian Wen, Sumant Sood  Abstract
Development Approach & Process Optimization for Sideall WLCSP Protection Lee J. Smith and Jun Dimaano Jr.  Abstract
Wet Cleaning as an Improved Final Quality Control of DRIE-Produced Features Meng Guo, Donald Pfettscher, Kimberly Pollard, Richard Peters, Travis Acra, Thierry Lazerand, Kenneth D. Mackenzie, Marco Notarianni  Abstract
Structural Integrity of a 3D TSV Package under Thermal Loading: A Structural Mechanics Based Study Mohammed Shahid Ali, B.E., A.R.Nazmus Sakib, B.E., Dereje Agonafer, Ph.D.  Abstract
Interposer Based Integration of Advanced Memories and an ASIC Muhammad Waqas Chaudhary, Andy Heinig  Abstract
Improving Device Yields and Throughput Using Plasma Dicing R. Barnett, D. Thomas, O. Ansell, J, Carpenter, W. Worster, G. Ragunathan  Abstract
A High Temperature Vapor Phase Polymer For Wafer-Level Packaging Rakesh Kumar, Ph.D.  Abstract
Advanced MEMS and Packaging: Photoresist, Adhesive and Thin Film Processing Solutions for Lift-Off Processing Richard Redburn, Kristen Gay, Matt Monroe, Garrett Oakes, Steven Sorrentino  Abstract
Stencil Design for Wafer Bumping/Wafer Level Ball Drop and Flip Chip Assembly for Wafer Bumping Susan Holmes and William E. Coleman  Abstract
Low Stress and Low Volatile Spin-On Dielectric Silicone Solution for Wafer-Level Packaging Thomas SELDRUM, Ph.D.; Byung K. Hwang, Ph.D.; Remington E. Fischer; Craig R. Yeakle; Maynard G. Hyer  Abstract
Methods for Assembly of TSV Products Tom Strothmann  Abstract
Optimization of Through Si Via Last Lithography for 3D Packaging Warren W. Flack, Robert Hsieh, Gareth Kenyon, John Slabbekoorn, Bert Tobback, Tom Vandeweyer, Andy Miller  Abstract
Assembly and Reliability Characterization of FCCSPS with Coreless Substrates and Copper Pillar Bumps Using No-Clean Fluxes and Mold Underfill (MUF) Weidong Liu, Guofeng Xia, Kui Wang, Lei Han, Ted Tessier, Daquan Yu  Abstract
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