DESIGN, MANUFACTURABILITY AND COST CONSIDERATIONS FOR BASEBAND AND MEMORY STACKED DIE SYSTEM IN PACKAGE SOLUTIONSAuthors: Jeannie Miller, Trent Thompson & Mark Gerber
Date Published: 5/15/2002 Conference: Telecom Hardware Solutions
This packaging technique has not presented a large number of challenges due to the memory dies having similar geometries, low pin counts, and functional requirements being similar. This report will discuss multiple challenges associated with combining high pin count semiconductor devices in a single package, specifically one base band ASIC processor with one or more memory devices. In addition, this paper will focus on four key multi-die packaging feasibility areas including early design, manufacturing, and cost considerations. It will also discuss future trends.
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