2003 HIGH DENSITY MICROELECTRONICS PACKAGING ROADMAP FOR SPACE APPLICATIONSAuthors: Lissa Galbraith, Ph.D.
Company: Jet Propulsion Laboratory/NASA
Date Published: 6/11/2002 Conference: Advanced Technology Symposium
Also needed is the development of 13 GHz laser drivers and amplifiers, evolving 10 Gb/s to be as affordable as 2.5 Gb/s, defining standard metallic or fiber interfaces for 10 Gb/s, as well as further development of receivers and transmitters to use wave division multiplexing for 10 Gb/s traffic. The American Optoelectronics Industry Development Association forecasts that by 2005 chip computational power will reach 9,800 MIPS, and the smallest package feature size will be 0.1 micrometers or less. Satisfying these demands will require enhanced electronic performance with an associated improvement in packaging performance and better relief from thermal and mechanical stresses.
Technical challenges and directions for high density interconnect microelectronics packaging also include understanding latent electromigration and dendritic growth, multilayer board hole wall wicking reliability issues, and characterization of reworkable underfill. NASA research with electronic noses, System-in-a-Package/System-on-a-Chip Technologies, and the identification of manufacturing processes, materials, quality, and reliability of embedded passive interconnects required for extreme temperature applications will be discussed. Technology challenges are described first for components, then the state of the art for high density materials and processes. Forecasts and recommendations for research direction are given for components, materials, and packaging.
Keywords: Roadmap, Packaging, Materials, Components, Predictions, Microelectronics.
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