Pan Pacific Symposium Conference Proceedings


Author: Vern Solberg
Company: Tessera
Date Published: 2/13/2001   Conference: Pan Pacific Symposium

Abstract: The market demand for chip-scale and chip-size BGA packaging for ICs is expanding rapidly. Proving to be fundamentally important to both current and future electronics, the array contact format is efficient for interconnect on the circuit board and the small component outline and lower profile (typical of these devices) is ideal for the higher component density electronic applications. The higher processing speed of today’s electronics requires a very direct signal path and interconnection between controller, processor and memory. The newest generations of Rambus RDRAM memory technology, for example, have been developed to be compatible with a special new chip set from Intel, furnishing processing speeds exceeding 1GHz, almost twice the speed of the PC processors.

To meet the need for packaging a silicon die for these faster processing speeds, Tessera has developed a two-sided copper, flexible polyimide film based interposer substrate employing laser ablated micro-vias. The chip-size package (unlike face-up wire bonded or direct chip attachment package structures), relies on the proven compliant BGA material system for both reliability and performance. The two metal layer interposer structure supplies a very direct die-to-ball contact interconnect and a robust ground plane within the finished package.

The following will outline the process steps and design attributes that enable the fabrication of one and two metal layer flex-based interposer and the die packaging process (step-by-step).

Key Words: BGA, BGA®, Chip Scale Packaging, CSP, Ball Grid Array, Fine Pitch Ball Grid Array, FBGA, RDRAM®, DDR SDRAM.

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