Pan Pacific Symposium Conference Proceedings


Author: James Rathburn
Company: Gryphics, Inc.
Date Published: 2/13/2001   Conference: Pan Pacific Symposium

Abstract: The current market trends in system level and package development are driving the use of large I/O count, high density packaging for high performance IC devices such as Microprocessors, ASICS, and Chipsets. As the IC device speeds and performance levels increase, significant issues arise related to the method and structure of package integration into the system level environment. From the perspective of mounting or attachment, a typical IC device of this type or nature encounters three major stages along the path to end-use in a system. Traditional methods of attachment such as adapters, sockets, connectors, or direct solder reflow have significant limitations and disadvantages when considering high speeds, large I/O area array devices from three perspectives within the life of the IC, and document the qualification of a new technology capable of achieving signal performance above 6-8 GHz. The intended discussion will establish the parameters of 3 separate development programs, each focused on a different stage of IC to system level integration. In each case, the signal performance of the device dictates that methods used one generation previous will no longer be acceptable. The first stage is related to the IC development level itself, conducted with involvement from Intel, and relates to the ability to maintain signal integrity while allowing for Chipsets and ASICs to be removed and replaced without solder reflow. The second stage is related to the System Level development from the perspective of the Enterprise Development Group at Compaq Computer Corp., where the ability to separably interconnect chipsets into the system provides significant advantages. The third state relates to a program with connector manufacturer Molex, where the need for high speed, high density integration is correlated from the IC and System Level development stages into low cost, high volume production use. The structure of the proposed paper is to define the requirements for each application, identify the critical need for a low parasitic connection between the device and the system circuit board, and document the results of qualification tests. Detailed attention will be paid to the critical interconnect issues encountered by Compaq, Intel, and Molex as they meet the challenges of next generation systems operating beyond 1-2 GHz.

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