Pan Pacific Symposium Conference Proceedings


Author: Ashish D. Alawani
Company: Conexant Systems, Inc.
Date Published: 2/13/2001   Conference: Pan Pacific Symposium

Abstract: The area array assembly process is extremely complicated due to the large number of material, equipment and process parameters involved. The intricacy has been enhanced by the increasing trend towards finer pitches and higher interconnects. The complexity of solder paste deposition increases with decrease in component pitch. The need for high assembly yields and product reliability, and the difficulties associated with rework have made tighter process control quite essential during area array assembly. That is why solder paste printing has become one of the most critical processes in area array assembly. There is not a single rule for stencil design and printing for area array packages. Due to the geometry and reliability differences, the level and nature of control is different for each of the different component types. Hence, developing a process for a variety of components together is a challenging task.

In the present research effort, the no-clean stencil printing process was studied and characterized for diverse, advanced surface mount packages including large Input/Output (I/O) Plastic Ball Grid Arrays (PBGAs), Ceramic Ball Grid Arrays (CBGAs) Chip Scale Ball Grid Array (CSBGA) and a Micro BGA (BGA). Additionally, printing was characterized for a Through-Hole Component (THC), which was to be reflow-soldered along with the area array components. The challenge was to identify a single stencil thickness and paste type for a diverse range of solder volumes with approximately 130,000 cubic mils of solder paste for the THC (with adequate hole-fill) at one extreme and at least 650 cubic mils for the BGA at the other. The approach used was to first find the optimal combinations for the sub-systems and then modify these combinations using mature consideration and calculated guesses to identify sub-optimal, but the most practical parameters for the entire system.

Multiple experiments were carried out using a Design of Experiments (DOE) based approach. Three different stencil thickness and two paste types were studied to identify the optimal materials for the overall system. The initial experiment identified that solder volumes as low as for the BGA can be deposited successfully using a Type III paste, provided the appropriate area ratios are maintained. This can be achieved by controlling the ratio between the aperture feature size and stencil thickness. The optimal thickness for the diverse range of components on the test vehicle used for the present research was identified to be 6 mils. Three different aperture shapes, namely, circular, oval and square with rounded corners were evaluated for paste transfer and in every single case circular apertures performed the best.

Adequate hole-fill could not be achieved for the THC by using a polyurethane squeegee. Hence, further experiments were conducted to establish a comparison between the print performances of a metal and a polyurethane squeegee. It was observed that the use of a metal squeegee increased the solder paste deposition at the area array sites by at least 20 - 30 % and resulted in a radical improvement in hole-fill (from 50 % previously) to 70 %. Comprehensive statistical analysis was performed to establish these findings. In summary, this paper comprehensively documents the various aspects involved in the development of a robust stencil printing process for a variety of interconnection technologies.

Keywords: Design of Experiments, Surface Mount Technology, Printed Circuit Boards.

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