Emerging Technologies Conference Proceedings


COST OPTIMIZATION OF HIGH DENSITY SUBSTRATES USING PLANAR RESISTORS

Authors: Daniel Brandler
Company: Ohmega Technologies
Date Published: 11/1/2000   Conference: Emerging Technologies


Abstract: Planar resistors are discrete thin-film resistive elements formed by standard printed circuit board print-and-etch processing. These resistive elements can be either surface or buried resistors in a multilayer printed circuit board or high density interconnecting substrate. Planar Resistor Technology (PRT) is used to create planar resistors and can be cost effective for high-density electronic applications, reducing the substrate cost as well as the surface mount (SMT) discrete component and assembly cost to achieve an overall cost reduction.

Standard cost models compare the fixed PRT area cost to the increasing SMT area cost to determine where increasing component densities make the use of PRT cost effective. Breakeven typically occurs between four and ten resistors per square inch of board area. However, standard cost models do not include other cost adders such as for High Density Interconnect (HDI) technologies that enable higher component and wiring densities.

Advanced technology cost models show that substrate and assembly metrics; component density, I/O density and wiring density are the primary determinates of the use of planar resistors for cost optimization. These advanced cost models show that PRT usage is indicated at complexity levels of 100 to 200 I/Os per square inch or interconnect densities of 100 to 160 inches per square inch. Continued use of discrete SMT resistors beyond this range drives up costs as increasing densities force the shift to more expensive interconnect technologies. These technologies shifts are (shown in order of increasing complexity):

1. Single-sided SMT changes to double-sided SMT, 2. Standard multilayer PCBs to sequentially built PCBs with buried vias, 3. Standard multilayer PCBs to HDI substrates with or without microvias. The switch to PRT occurs as an alternative to higher cost sequential build PCBs or HDI substrates needed to interconnect with the SMT resistors. Embedding resistors in existing layers and using conventional PCB technology reduces the cost of the substrate. PCBs using embedded planar resistor technology are less expensive than comparable designs using HDI and SMT chip resistors. The cost advantages of PRT are:

1. Reduced substrate area costs resulting from smaller form factors, 2. Reduced substrate conversion costs (added layers, build-up and/or HDI costs), 3. Reduced discrete SMT component and assembly costs.

For cost optimization, the cost of a PCB using buried resistors must be compared to the cost of alternative technologies that enable continued use of SMT components. Planar resistor costs adders are approximately $.25 per square inch per layer. Where the area cost increase of an alternative design exceeds this amount, the use of PRT is indicated.



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