SMTA International Conference Proceedings


Author: Pennanen Virpi
Company: Nokia Telecommunications
Date Published: 9/12/1999   Conference: SMTA International

Abstract: Due to the demand of increasing I/O counts and thermal performance requirements in complex ASICs, BGA type packaging concepts are fast gaining popularity in applications. Unfortunately, these new concepts cannot be accepted without exhaustive testing needed to guarantee 20 years reliability in a demanding telecommunications environment. This rapid invasion of BGAs makes a thorough testing of all available packages impossible. Use of various modelling tools is an obvious way to save resources by discarding the most unreliable solutions before wasting testing capacity.

A testing procedure was created and then evaluated in the following manner. Two different manufacturers' TBGA256 components were assembled on Ni/Au and OSP finished test boards using SMD and NSMD pad design. The assembled boards were temperature cycled (-40…+125 °C) until at least half of them had failed. Parametric 3D FE-models of the components were generated and the simulated 'cycles-to-failure' results were compared against thermal cycling test results. After this verification of the FE-models, environmental conditions were added to assess the life times of the assemblies in the targeted environment. Also the sensitivity of the 'assembly use life' to assembly parameters such as PCB properties were evaluated.

Some differences in TBGAs board level reliability were found and therefore they stand for an excellent benchmark for future CSP reliability testing. Minor differences were found in pad design (SMD pads were better than NSMD) and in board finishing (OSP were better than Ni/Au). With all combinations first failures happened after 1000 cycles. FE-modelling combined with accelerated stress testing proved to be an effective tool for test result analysis and rationalising the test sequences.

KEY WORDS: TBGA, reliability, FEM

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