Process Development Challenges and Design of Experiments for Conformally Coated Printed Circuit Board Assemblies
Authors: R. Muralidharan, R. Dhiman, D. Santos, K. Srihari, C. Greene, B. DeKelaita, G. Pandiarajan, S. Eckel Company: SUNY Binghamton University and SMART Modular Technologies Date Published: 9/22/2019
Abstract: This study presents the various challenges involved in a large-scale automated spray conformal coating process for memory modules. A custom, in-house conformal coating process was improved based on the foundations laid out by prior process analyses and design study. The study showed support for acceptable levels of cleanliness, surface energy, improved wettability, and coverage of the coating material on the varied topography of the SODIMM (Small Outline Dual In-line Memory Module). During the development of the internal coating process, other issues emerged as process challenges. These issues included bearding, overspray, and foreign object debris (FOD) on module surface. These challenges were resolved by modifying the spray dwell-purge techniques and the fixture. In order to identify the optimum conformal coating parameters a general factorial experiment was conducted. Three factors were taken into consideration: coating material to thinner Mixing Ratio, Atomizing Pressure, and Micrometer setting. The factorial analysis used two replicates. Results indicate that optimum thickness can be obtained at a Mixing Ratio of 3:1, Atomization Pressure of 3.5psi, and at Micrometer setting of 400µm. Further tests were conducted to test the reliability of the coated module per IPC-HDBK- 830A, IEC, and other related JEDEC standards.