Root Cause Stencil Design for SMT Component Thermal LandsAuthors: Greg Smith and Tony Lentz
Company: BlueRing Stencils and FCT Assembly
Date Published: 9/22/2019 Conference: SMTA International
The IPC 7525B Stencil Design Guideline  recommends a 20% to 50% reduction in the printed area of the thermal/ground plane for leadless chip carrier (LCC) / bottom terminated component (BTC) devices which is a very broad window. This guideline also recommends the window pane design for printing these thermal lands but does not specify the size of the gaps between panes. It also does not specify how close these panes can be printed to the edge of the thermal land without creating shorts to the perimeter leads or creating solder balls on components such as Decawat Packages (D-Pak). This window pane stencil design remains the most used design for the reduction of paste on thermal pads as many other designs such as rounds, diamonds, diagonal pads etc. have not been shown to dramatically impact voiding percentages.
This paper specifically explores the effect of the window pane design on void area percentage after reflow for surface mount technology (SMT) component thermal pads without introducing float to the component. Specific window pane gap sizes, total area printed and distance of the outer pane edges to the copper thermal land edge will be varied to determine guidelines for thermal pad stencil design.
BTC, LCC, stencil design, window pane, voiding
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