Void Reduction in Reflow Soldering Processes by Sweep Stimulation of PCB Substrate – DoE TestsAuthors: Viktoria Rawinski, Joe Clure, Marcel Buck and Denis Jean
Company: Kurtz Ersa Group and Kester Inc.
Date Published: 10/14/2018 Conference: SMTA International
Production speed and throughput are of central importance after the implementation of the industrial application. Besides the right choice of solder paste and soldering profile the right setup parameters are crucial. To make the correlation of different parameters in the voidfree process visible a DoE test was carried out in order to obtain the right setup parameters for a product as fast and efficiently as possible. For carrying out the tests QFN and MLF components were placed on the PCBs. DoE tests are a good method to evaluate the influence of different parameters by a statistical test procedure and to visualize their varied correlations in no time. Especially two parameters of the voidless process stand out in the experiment, which individually as well as in combination significantly influence the process. These are the influence of the actuation elongation on the PCB level as well as the sweep width. The performed tests have shown that the influence of the actuation elongation has the biggest effect on the void reduction and that it should be used as the first setup parameter for optimizing the void reduction results.
voidless, void reduction, DoE tests, sweep stimulation, reflow process
Members download articles for free:
Not a member yet?
What else do you get when you join SMTA? Read about all of the benefits that go along with membership.
Notice: Sharing of articles is restricted to just your immediate work group. Downloaded papers should not be stored on an external network or shared on the internet.