Practical Verification of Void Reduction Method for BTC Using Exposed Via in PadAuthors: Alfredo Garcia, Domingo Vazquez, Ricardo Macias, Rodrigo Ibarra, Joe Smetana, Mulugeta Abtew, Iulia Muntele
Company: Sanmina and Nokia
Date Published: 10/14/2018 Conference: SMTA International
The method explored in this paper regards the use of exposed via in pad. A dedicated test vehicle was designed for two types of QFN components. The main variables taken into account were the component size, number of exposed via in the thermal pad, via pitch, via size, and solder paste coverage. The responses sought in this experiment include thermal pad void level and solder wicking down the via barrel with resulting solder protrusion on the opposite side of the PCB.
The results indicated that solder will wick down the exposed via in pad regardless of the via diameter and solder paste coverage. Despite this finding, there were no defects recorded like component tilting, skewing, opens, or solder bridging. Specific configurations attained voiding levels in the thermal pad below 25%; however, other configurations did show void level for the thermal pad up to 50%. A discussion will be presented regarding the effect of the board thickness and the geometry of the via array on the thermal pad solder coverage and voiding level.
BTC, PTH, void, lead free
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