IWLPC (Wafer-Level Packaging) Conference Proceedings


Heterogeneous Integration by Collective Die-To-Wafer Bonding

Authors: Thomas Uhrmann, Jürgen Burggraf, Martin Eibelhuber
Company: EV Group GmbH
Date Published: 10/23/2018   Conference: IWLPC (Wafer-Level Packaging)


Abstract: As Moore's law is running out of steam, advanced packaging has taken leadership to drive performance. On the one hand, the die area is constantly reduced especially for small package sizes and heterogeneous integration with high interconnect density becomes crucial. This is for example the case in IoT or mobile applications. On the other side, for large packages sizes heterogeneous integration and die segmentation gets an increasing role of processing applications. Here, heterogeneous integration leads to an overall increased yield, mainly as smaller dies generally can be produced with higher yield. In the same time and most importantly, memory, processors, sensors and such from different sources can be combined using heterogeneous integration.

Combining segmented dies in an advanced package can be done by two different bonding technologies, namely sequential die bonding or a collective die bonding approach. For the collective bonding, individual dies are populated and tacked either on an interposer or a so-called handling carrier, depending on the bonding technology applied. In case of tacking die face-down on an interposer or other active silicon die, bonding is usually being done by thermal bonding. Here, heating and cooling of the substrates are only done once, considerably reducing process cost and thermal budget of the underlying substrate. The second case is tacking the dies face up on a carrier substrate. This reconstructed dies on a carrier can now be processes again on wafer scale, this means preprocessing steps such as direct bonding can be done before bonding the wafers using fusion or hybrid bonding.

In this paper, we will show different integration approaches for collective die bonding for both thermal bonding as well as fusion / hybrid bonding. For both processes, results in terms of die placement and sequential alignment accuracy of the integrated process will be compared and discussed, together with current and potential applications of these processes for future devices.

Key Words: 

Heterogeneous Integration, Collective Die-to-Wafer Bonding, Hybrid Bonding, Fusion Bonding, 3D Integration



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