Effect of Package Warpage and Composite Cte on Failure Modes in Board-Level Thermal CyclingAuthors: Andrew Mawer, Paul Galles, Mollie Benson and Burt Carpenter
Company: NXP Semiconductors
Date Published: 10/14/2018 Conference: SMTA International
This paper will give examples of the BLR TC failure modes and locations of various package test vehicles that were designed to attempt to correlate those failure modes to the in plane CTE and out of plane warpage behavior of those packages. BLR TC results will be presented in Weibull format along with failure analysis using both cross-sectioning and dye penetrant analysis.
Package CTEs were measured using Digital Image Correlation (DIC) and package warpage over approximately the same temperature range as TC was measured using CoolMoiré, a Shadow Moiré technique that brings the sample to temperatures as low as -55ºC. The results show that by knowing both the warpage and CTE behavior of packages, the board mounted TC failure location, and to lesser extent, the relative performance, can be better understood. The two package types that will be studied are flip chip PBGA (FC PBGAs) and overmolded, wire-bonded PBGAs with various die sizes.
Solder Joint Reliability, SJR, Board Level Reliability, BLR, Coefficient of Thermal Expansion Mismatch, CTE, TherMoiré, CoolMoiré, Shadow Moiré, Interferometry, Digital Image Correlation, DIC, Package Warpage, Ball Grid Array, BGA
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