IWLPC (Wafer-Level Packaging) Conference Proceedings

A Practical Guide for First-Time FOWLP Design Success

Authors: Kevin Rinebold, John Ferguson, Keith Felton
Company: Mentor, A Siemens Business
Date Published: 10/23/2018   Conference: IWLPC (Wafer-Level Packaging)

Abstract: New, emerging, and existing markets demand ever- smaller electronic devices that surpass the performance of their physically larger predecessors with thinner and smaller form factors and lighter, increased functionality with faster data transfer, without sacrificing battery lifetime and affordability. Fan out wafer level packaging (FOWLP) is fast becoming the new die and wafer level packaging technology of choice for the next generation of compact, high-performance electronic devices, fulfilling the above requirements with higher I/O interconnect density and packages with multi-layer redistribution lines (RDL) with finer line/space widths. The versatility of FOWLP technologies provides the ability to expand into 3D packaging architectures such as multi-chip, system-in- package (SiP) assembly, and package-on-package (PoP) configurations.

Implementing a unified FOWLP design approach requires a significant expansion in communication between the IC design world, the package design world, and a new dimension, that of communication and interaction with the OSAT/Foundry that will fabricate and assemble the complete device. FOWLP, as with other emerging High Density Advanced Packages (HDAP), have unique and often restrictive/strict rules and guidelines, a hybrid combination of traditional ASIC and organic packaging worlds.

This paper will explore best-practice approaches for embarking on FOWLP design, including how to leverage your Foundry or Outsourced Substrate Assembly and Test (OSAT) partner, and how to ensure your design is manufacturable the first time to avoid expensive and time-consuming changes.

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