IWLPC (Wafer-Level Packaging) Conference Proceedings

High Density and High Bandwidth Chip-To-Chip Connections with 20µm Pitch Flip-Chip on Fan-Out Wafer Level Package

Authors: A. Podpod, D. Velenis, A. Phommahaxay, P. Bex, F. Fodor, EJ. Marinissen, K. Rebibis, A. Miller, G. Beyer and E. Beyne
Company: Interuniversity Microelectronics Center (IMEC)
Date Published: 10/23/2018   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Various Fan-Out Wafer Level Packaging (FO-WLP) approaches have been developed and established over the past years to answer the increasing need for high data rates, wide I/O count and the demand for increase function integration on package.

Imec has been working on a novel 300mm FO-WLP concept that enables 20µm pitch interconnect density: Flip-Chip on FO-WLP. Major challenges and solutions are reported in this paper. Results demonstrate die placement alignment of <3µm, which is suitable to allow stacking for high density interconnect. Connections between the assembled dies were intact before and after molding.

Key Words: 

Fan-Out, Wafer Level Package, Heterogenous Integration, Flip Chip, warpage, die shift, wafer molding, ultra-high density

Members download articles for free:

Not a member yet?

What else do you get when you join SMTA? Read about all of the benefits that go along with membership.

Notice: Sharing of articles is restricted to just your immediate work group. Downloaded papers should not be stored on an external network or shared on the internet.


SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344 USA

Phone +1 952.920.7682
Fax +1 952.926.1819