IWLPC (Wafer-Level Packaging) Conference Proceedings


Multiscale Models for Electroplating of Through Silicon Vias

Authors: K. H. Khoo, Lai MingRui, H. Ramanarayan, J. Hongmei, S. Wu, C. A. Joshi, K. R. Mangipudi, J. J. Cheng, S. S. Quek, D. T. Wu, N. Sridhar, M. S. Bharathi
Company: Institute of High Performance Computing, National University of Singapore, Indian Institute of Technology, Institute of Materials Research and Engineering
Date Published: 10/23/2018   Conference: IWLPC (Wafer-Level Packaging)


Abstract: We present multi-scale models providing guidelines for defect free growth of filling of through silicon vias (TSV) by electroplating. Using first-principles calculations, we understand the chemistry of the electroplating process. We use density functional theory calculations to identify the reaction mechanisms and calculate the reaction energies of the different additives i.e., chloride ion, suppressor, and accelerator in the plating solution. We also present a kinetic Monte Carlo model that can incorporate the chemical and transport properties of the ions and additives during the electroplating. We demonstrate the role of aspect ratio and attachment rates on defect-free bottom-up filling. These multiscale tools can provide the inputs for a continuum phase field model to predict the microstructure during TSV filling (not reported here).

Key Words: 

Through silicon via, multiscale modelling, DFT calculations, kinetic Monte Carlo



Members download articles for free:

Not a member yet?

What else do you get when you join SMTA? Read about all of the benefits that go along with membership.

Notice: Sharing of articles is restricted to just your immediate work group. Downloaded papers should not be stored on an external network or shared on the internet.


Back


SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344 USA

Phone +1 952.920.7682
Fax +1 952.926.1819