Chip Board Interaction Analysis of 22-nm Fully Depeleted Silicon on Insulator (FD-SOI) Technology in Wafer Level Packaging (WLP)Authors: Jae Kyu Cho, Jens Paul, Simone Capecchi, Dirk Breuer, and Frank Kuechenmeister, Doug Scott, JongJin Choi, and Wonjoon Kang
Company: GLOBALFOUNDRIES and Amkor Technology
Date Published: 10/23/2018 Conference: IWLPC (Wafer-Level Packaging)
In this article, to systematically address the CBI, a large test vehicle based on 22-nm fully depleted silicon on insulator (FD-SOI) technology platform and WLP technology is described. In particular, CBI during drop test and temperature cycle on board is investigated and its failure mode analysis is discussed. The impact of silicon die thickness and ball grid array (BGA) metallurgy is also explored.
Wafer Level Packaging (WLP), Redistribution layer (RDL), Chip Board Interaction (CBI), Drop test, Temperature Cycle on Board (TCoB) test
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