IWLPC (Wafer-Level Packaging) Conference Proceedings

Low-Density Fan-Out SiP for Wearables and IoT with Heterogeneous Integration

Authors: A. Martins, M. Pinheiro, A. F. Ferreira, R. Almeida, F. Matos, J. Oliveira, Eoin O'Toole, H. M. Santos†, M. C. Monteiro, H. Gamboa, R. P. Silva
Company: Fraunhofer Portugal AICOS, INESC TEC, and AMKOR Technology Portugal, S.A.
Date Published: 10/23/2018   Conference: IWLPC (Wafer-Level Packaging)

Abstract: The development of Low-Density Fan-Out (LDFO), formerly Wafer Level Fan-Out (WLFO), platforms to encompass the requirements of potential new markets and applications such as the Internet of Things (IoT) is crucial to maintain LDFO as the leading Fan-Out technology. This drives the development of a new set of capabilities in the current standard LDFO process flow to break through the existing technology boundaries.

One of the most widely discussed advantages of LDFO packaging is heterogeneous high-density system integration in a package. LDFO System in Package (LDFO SiP) integrates active dies, passive components and even already-packaged components using other packaging technologies. This heterogeneous integration is based on a wide range of different geometries and materials placed inside the LDFOSiP with high accuracy.

Ultimately, heterogeneous integration will be fundamental to achieve new levels of miniaturization. However, multi-die solutions face several challenges such as bare-die availability, passives integration, antenna integration, low power budget, test complexity and reliability.

Package research and development (R&D) must overcome all of these issues to build a product with high volume manufacturability. The wafer level SiP (WLSiP) technology required to enable the new features and processes needs to be ready for high volume manufacturing of new products at high yield and reasonable cost.

This paper presents the approaches used to effectively enable LDFO SiPs (WLSiPs):

1. A pre-formed vias solution is employed to connect front to back side of the package, including development for high accuracy via bar placement.

2. A wafer front-side to back-side redistribution layer (RDL) alignment solution was developed.

3. Space requirement reduction between components to achieve the smallest possible package.

4. Miniaturized Bluetooth antenna integration in the RDL.

5. Creation of a stacking concept (vertical connections to create a modular system that enables easy addition of new features to the final product).

Inside the package (excluding the area reserved for the antenna), components are densely packed: several sensors, power management components, radio communication and all required passives are incorporated into a single WLSiP. Connecting all these features to create a component that works by connecting only a single battery required implementing a double sided, multi-layer RDL, while maintaining the ability to create a 3D solution by stacking vertical connections for several other solutions. The result is an approach that easily adapts the system to a variety of customers’ needs.

The work done is part of the collaborative COMPETE2020-PT2020 funding program under "IoTiP- Internet of Thing in Package" project nº 017763, Projetos de I&DT Empresas em CoPromoção.

Key Words: 

LDFO, LDFO SiP, Fan-Out WLP, WLSiP, SiP, Multi-Chip-Package, Antenna-in-Package, Package-on-Package, Through Mold Via, TMV®, TPV

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