IWLPC (Wafer-Level Packaging) Conference Proceedings

Board Level Reliability Study of Next Generation Large Die Wafer Level Chip Scale Package Structures

Authors: Timo Henttonen, Paul Mescher, Doug Scott, Han Park, YongJae Ko and Kevin Engel
Company: Microsoft and Amkor Technology
Date Published: 10/23/2018   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Wafer Level Chip Scale Package (WLCSP) technologies are being used more often in electronic components due to their smaller size and lower cost, and are being applied to larger die and ball matrix sizes. Originally implemented mainly in mobile devices (i.e., smartphones), WLCSP components are now frequently used in new product categories that have more stringent use conditions than the mobile space. The harsher use conditions raise a concern of solder joint reliability, especially in temperature cycling due to the difference in the coefficient of thermal expansion between the silicon die and the laminate motherboard. While cycle life can be extended by using underfill, underfilling makes the surface mount assembly process more complex and costly, increases cycle time and inhibits rework.

To solve the challenge of extending cyclic life without underfill, new WLCSP structures and materials have been proposed. This paper describes the investigation of some of these innovative solutions through motherboard assembly and board level reliability testing. The package variables consisted of two WLCSP structures utilizing ball support mechanisms and a Bismuth (Bi) bearing solder ball that is expected to increase fatigue life.

Packages were produced separately with each variable, along with legs that included both new packages and new alloy. The finished assemblies, along with a control leg of standard structure/solder, were subjected to drop testing and temperature cycling. Solder joint integrity was monitored in-situ to accurately identify duration to failure for Weibull analysis.

The results clearly show that this new generation of WLCSP structures can offer dramatically improved fatigue life without a significant sacrifice in drop reliability. This benefit should allow the use of WLCSPs in more challenging environments, as well as providing designers the option of using larger package sizes in existing mobile designs.

Key Words: 

Wafer Level Chip Scale Package (WLCSP), board level reliability (BLR), temperature cycling, drop test, SACQ, SAC

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