SMTA International Conference Proceedings


Development of High Density Interconnect Technologies for Panel Level Packaging

Authors: Lars Boettcher, S. Kosmider , Friedrich-Leonhard Schein , and Andreas Ostmann
Company: Fraunhofer Institute for Reliability and Microintegration (IZM) Technical University of Berlin
Date Published: 10/14/2018   Conference: SMTA International


Abstract: Advanced packaging technologies like wafer-level fan-out and 3D System-in-Packages (SIPs) are rapidly penetrating the market of electronic components [1]. A recent trend to reduce cost is the extension of processes to large manufacturing formats, called Panel Level Packaging (PLP). In a consortium of German partners from industry and research advanced technologies for PLP are developed. The project aims for an integrated process flow for SIPs with chips embedded into an organic laminate matrix.

At first dies with Cu pad metallization with 100µm contact pitch are placed into openings of a laminate frame layer with very low coefficient of thermal expansion (CTE). They are embedded by vacuum lamination of thin organic films, filling the very small gap down to 15µm between chips and frame. The frame provides alignment marks for a local registration of following processes. The ridged frame limits die shift during embedding and gives a remarkable handling robustness. Developments are initially performed on a 303x227mm² panel format, aiming for a final size of 610x615mm². On the top side of the embedded chips, a 20µm dielectric film is applied. Micro via to the chip contacts as well as high aspect ratio blind vias around the chip to lower interconnect layers are formed by UV laser drilling. The formation of fine, high aspect ratio, laser drilled vias is an essential technology step. Another way would be an approach which avoids drilled via connections and realizes a direct contact to the RDL lines.

Conventional metallization sequences, like thin copper foils as base and electroless or direct copper metallization of vias, are not suitable for high density routing demands. That’s why as the following step TiW/Cu or Ti/Cu barrier and seed layer is applied by sputtering. Subsequently high resolution photoresist is applied and exposed by a newly developed Direct Imaging (DI) system. Lines and spaces of 4µm were already achieved. In the following, Cu is simultaneously electroplated for via contacts and interconnects traces.

Finally, the photo resist is stripped and the TiW or Ti barrier and Cu seed layers are etched. The paper will discuss the new developments in detail, with the focus of a new developed technology sequence.



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