Copper Pillar Plating Systems High Speed - Low HeatAuthors: E.Walch, DJ., C.Rietmann, Ph.D., A.Angstenberger, Ph.D.
Company: MacDermidEnthone Electronic Solutions
Date Published: 9/17/2017 Conference: SMTA International
Commonly used packaging concepts comprising waferlevel plating, through-silicon-vias (TSV), redistribution layer design (RDL), intermediate pillars, macrobumps and copper filled through holes in the final circuitry are being roughly sketched followed by an overlook of the extremely different pillar geometries within each packaging level posing individual challenges on the copper plating chemistry and process. Practical aspects namely dialling in the chemistry additives and process windows to match the relevant applications´ needs will be shortly reported, the ongoing R&D work targeted for current and future requirements to be presented.This paper concludes with actual research results on achievable copper textures and the subsequent performance of the plated copper interconnects as far as crystal lattices, and the related thermal reliability are concerned.
copper pillar plating, thermal vias, plating additives, copper texture, copper reliability
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