SMTA International Conference Proceedings

Contact Interconnect Challenge and Resolution The Ddr4 Dual-Contact Methodology, Component and Board Level Reliability

Authors: Paul Wang, Ph.D., David He, Rocky Wang, Alien Jiang, DF Chung, Shigeyuki Takizawa, Fred Ge, Orson Wang, Fred Ye, Park Liang, KG Tan
Company: MiTAC Computer Corp., Fujitsu Component Limited, Inspur Electronic Information Industry Co.
Date Published: 9/17/2017   Conference: SMTA International

Abstract: This article is Part 3 of a series of studies on new generation of electronic contact challenges and component interconnects technology for high-end computer products. These products include server and data storage for cloud computing applications at the data center as well as core routers for service providers, edge and branch routers for enterprise networking companies, and small switch and wireless router for commercial and small and home office. All these cloud computing products require high data speed in terabytes per second and high signal integrity for the massive mobile users and IoT application whenever and wherever they wish to connect.

To achieve such mobility and signal integrity the major focus is the electrical interconnections between the CPU/GPU and component in the system. Due to the large number of edgecard connections such as DIMM, PCIe, etc. in modern computer systems and due to their relatively low reliability, in previous Part 2 of the study a test vehicle with daisy chain was used to assess the contact interconnect failure related to factors such as soldering flux residue, plating quality, contact interface cleaning and doubt insertion, and particulate control and management. As concluded in Part 2, the heavy flux residue and vibration pre-conditioning have medium effect on contact failure, however contact interface cleaning and particulate control show no significant contribution and not able to eliminate the last thousands DPPM of DIMM contact failure.

The purpose of current Part 3 of the study is to look into a new generation of dual-contact interconnect methodology and assess component level contact configuration and interconnect reliability. First, the contact pin configuration and plating morphology such as homogeneity and thickness are carefully examined to ensure contact integrity between DDR4 connect and DIMM module can be achieved. Then normal force of dual-pin and separated single-pin from the whole were measured to benchmark to existing conventional singlecontacts. Furthermore the JEDEC Raptor test vehicle was adapted to assess contact impedance and four signal integrity tests, RL (return loss), IL (insertion loss), NEXT (near-end cross talk), and FEXT (far-end cross talk) to ensure signal integrity requirements are fulfilled. Finally, board level reliability test is proposed for Raptor test board and trial run on real product. The overall goal of Part 3 of the study is to ensure a smooth migration from conventional single-contact to a new interconnect mechanism with robust board and system reliability for high signal integrity requirement in cloud computing and IoT application.

Key Words: 

Networking product, cloud computing, IoT, mobility, component reliability, DDR4, DIMM, contact interconnect, manufacturing environment, particulate control and management, dual-contact, signal integrity, normal force, characteristic impedance, Raptor, board level interconnect, board reliability

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