SMTA International Conference Proceedings

The Next Generation of 3D Packaging Using a Glass Interposer

Authors: C. G. Woychik, F. D. Egitto, D. Bajkowski, M. Gaige, W. Wilson, A. Shorey
Company: i3 Electronics, Inc., Precision Glass Solutions, Corning Incorporated
Date Published: 9/17/2017   Conference: SMTA International

Abstract: Today most interposers used for 2.5D packaging are made of silicon. This is mainly driven by the ability to utilize existing mature copper back end of line (Cu-BEOL) technology in the semiconductor fabrication facility to do the necessary fine line redistribution. TSMC has been very successful at using their Chip-on-Wafer-on-Substrate (CoWoS) technology to assemble 45um pitch die having solder capped Cu-pillars to a Si-Interposer having through silicon vias (TSVs) in a semiconductor clean room environment. However, the industry would like to see more of this type of advanced assembly returning back to the conventional packaging assembly and test facility. Here i3 Electronics will utilize their expertise in panel processing to manufacture a low-cost glass interposer. In this work i3 has developed a process to produce through glass vias (TGVs) in a 300um thick substrate. Both sides are metalized with 25um lines and spaces. The design will accommodate double-sided component attach. The process flow to build this interposer and the challenges in developing a high volume panel process for a glass interposer will be discussed.

Key Words: 

Si-interposer, 2.5D, through glass via (TGV), high density interconnect (HDI), semi-additive plating (SAP).

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