Optimizing Package Tilting And BLR Performance Through PCB and Stencil Design for Son Packages
Authors: Andy Zhang, David Chin, Steven Kummer Company: Texas Instruments, Inc. Date Published: 9/17/2017
Abstract: Small Outline No-lead (SON) packages have gained popularity since recent years thanks to their enhanced thermal performance through exposed thermal pads and optimal electrical performance due to the leadless land pattern. However, they are more prone to package tilting than QFN packages are due to the fact that SON package has solder joints on only two sides of the package, instead of all four sides in the case of QFN. Board Level Reliability (BLR) performance could be compromised as a result of package tilting. A carefully designed PCB land pattern and stencil, along with other aspects in the SMT process such as paste printing, reflow profile and cooling rate, could minimize package tilting after reflow and ensure the designed BLR performance. In this research, PCBs with various land pattern dimensions and stencil opening dimensions were used for a 3x3 mm 0.5 mm pitch SON package. Anchor pins on the non-IO sides of the SON package were added to try to balance the package. Package tilting was characterized by measuring the heights at package corners. Realtime video showing the movements of the package during reflow was captured. BLR temperature cycle test was conducted subsequently to obtain the Weibull data under various scenarios. The effects of PCB land pattern, stencil opening, anchor pins, reflow profile, on package tilting and BLR performance are discussed.