Emerging Technologies Conference Proceedings


RELIABILITY EVALUATION OF ULTRA CSPTM PACKAGES

Author: Hong Yang
Company: Flip Chip Technologies
Date Published: 11/16/1998   Conference: Emerging Technologies


Abstract: CSP packages offer the solution for miniaturization using conventional surface mount assembly equipment. Currently there are three important factors that influence the industry-wide acceptance of CSP packages: cost, reliability, and board technology development. A comprehensive reliability evaluation of the Ultra CSPTM packages from 0.50 mm pitch to 0.80 mm pitch is presented. Three Design-of-Experiment(DOE) case studies were conducted for design optimization. The CSP package, called Ultra CSPTM, is developed using “CSP” size solder balls and modified redistribution process to reroute the pads to JEDEC standard pitches. Specific devices tested are a daisy chain device with 90 I/O and 0.80 mm pitch, a daisy chain device with 46 I/O and 0.75 mm pitch, a 0.65 mm-pitch daisy chain device with heating and temperature sensing capabilities and a 0.50 mm-pitch daisy chain device with heating and temperature sensing capabilities. The reliability tests include thermal cycle, high temperature storage, temperature/humidity/bias, and high temperature operating-life tests. Reliability characteristics of the packages are presented. Discussions on assembly, testing sockets, and board development are also provided. Key Words: CSP, Chip Scale Package, wafer level packaging, Ultra CSPTM, flip chip, bumping, wafer bumping, redistribution, BCB



Members download articles for free:

Not a member yet?

What else do you get when you join SMTA? Read about all of the benefits that go along with membership.

Notice: Sharing of articles is restricted to just your immediate work group. Downloaded papers should not be stored on an external network or shared on the internet.


Back


SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344 USA

Phone +1 952.920.7682
Fax +1 952.926.1819