SMTA International Conference Proceedings


Failure Analysis of Small Form Factor Devices

Authors: Priyanka Dobriyal, Lauren Cummings, Chet Lee
Company: Intel Corporation
Date Published: 9/17/2017   Conference: SMTA International


Abstract: As wearables and Internet of Things (IoT) devices gain consumer popularity, there is a growing trend in package miniaturization. A variety of thin and high-density technologies are gaining momentum in industry, including direct chip attach (DCA), the wafer-level package (WLP), and system-in package (SiP). Due to their small form factor and complex integration, these technologies pose a challenge for failure analysis (FA), particularly after board assembly. Conventional board-level FA techniques—such as dye-and-pull and cross-section—can destroy the true failure signature by inducing cracks or delamination. Even newer FA techniques—such as X-Ray computed tomography—can be time-consuming, and sometimes incapable of identifying subtle cracks or solder extrusions.

This paper addresses the FA challenges encountered for two separate SiP and WLP functional failures. Board-level FA and package-level FA techniques were leveraged for root cause findings, and process improvements were made to preserve the defect signature.

Key Words: 

Failure analysis, WLP, SiP



Members download articles for free:

Not a member yet?

What else do you get when you join SMTA? Read about all of the benefits that go along with membership.

Notice: Sharing of articles is restricted to just your immediate work group. Downloaded papers should not be stored on an external network or shared on the internet.


Back


SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344 USA

Phone +1 952.920.7682
Fax +1 952.926.1819