So what's Moore's Law to semiconductor packaging? Is this an attempt to miniaturize every semiconductor component in order to fulfill it or it is a forecast and observation of what is becoming and future of electronics and all things inside of it and its environment. In 1965, Mr. Gordon Moore of Intel made an observation that the number of transistors per square inch in IC is doubled every year since the invention of solid state. Along the way, the timing shifted to every 18 months and it became the guideline of packaging development. So that in every around 18-month period, higher density, smaller wafer and higher performing dies were coming out of semiconductor fab houses. Consequently, packaging houses have to follow suit wherein materials have to change, process techniques have to be sophisticated and assembly equipment has to perform with more intricacies. Taking for instance in the wafer fabrication, the track features or nodes were reduced from micrometer to nanometer in order to put more circuitry in IC. The latest discussion on die thickness is now at 50 um when before 200 microns was the norm. In packaging realm, plastic package using leadframe as the carrier started to be in Dual-in-Line Package to Quad Flat Pack Leaded Array, from leaded package to leadless IC, these are all indicating higher density I/O in the same form factor. IC packaging nomenclature such as PDIP, PLCC, QFP, SOP, BGA, uBGA, QFN, CSP, WLCSP, FOWLP and so on present high counts of input/output terminals and high performance device packed in small housing. Further scrutiny what's inside shows interconnection between dies and substrate is not only limited to wirebonding where dies are mounted face up with its connection made from the periphery. Recently, increasing flip chip technology offers more interconnection by having array of bumps within the body thus increasing the density of circuit connections. Even the wire materials are changing from 50um to 38um to 25um and 15um to accommodate tight wire spacing, bumps change from solder to Cu-pillar to achieve the same. Substrate thickness is decreasing to the point that there is a substrate-less packaging technology that is becoming significant it the semiconductor industry. On the other hand, substrate manufacturer cannot be denied and has to re-invent its importance by embedding discrete passive components and even dies before passing it to packaging house. It can be imagined that in this packaging evolution, process techniques will have to adapt. Precision placement and accuracy will be tighter. Lateral movement and rotation of active and passive components have to be very limited or else, electrical shorting will be imminent. Also, as these components became thinner and smaller, it became fragile and component has to be handled very delicately. With this process requirements, one has to think that it has to be done slowly and with a lot of cautions. If that will be the case, productivity will be lost and therefore cost of production will be higher. In this paper, these factors about process criticality and manufacturing productivity shall be looked into. Not only that, flexibility in solution when multiple different dies in wafer form has to be mixed up with passive components to be processed in single pass will be also be presented. In addition to it, there will be a discussion about producing more parts as a factor of large working area. There will be more to it when advanced packaging has to be discussed, it will include 2.5D, 3D, SiP, FanOut,C2W and many more.