Authors: Sheng-Hung Chou¹ Jonas Sigfrid Sjoberg¹ Sze Pei Lim¹ Maria Durham¹, Te-Hua Fang, Ph.D.², and Yu-Jen Hsiao, Ph.D.³ Company: Indium Corporation¹, Department of Mechanical Engineering, National Kaohsiung University of Applied Sciences², National Nano Device Laboratories³ Date Published: 3/28/2017
Abstract: The system-in-Package (SiP) module market has grown significantly over the past several years and it is now one of the fastest growing packaging technologies in the semiconductor industry driven by lower cost, smaller form factor, higher levels of integration and better performance. SIP is capable of packing more functionality into a single package with a small form factor. This continues to push miniaturization to an even greater level, therefore creating assemblies with smaller components and greater density. The passive components push from 0201 to 01005 now and the industry is looking at utilizing 008004 passive components for the next generation SiP. All of these changes bring lots of challenge to the SMT process and yield loss. The major yield loss is tombstone and HIP defect. In order to get better yield performance there are many process factors need to control such as reflow profile optimizations, metal load%, flux oxidation barrier, printing consistency, components placing accuracy, stencil design and components surface coating. In this work some study had been tested on the reflow profile (standard vs. soaking), metal load% and components surface contamination by using Auger electron spectroscopy (AES) analysis. Five different flux formulations with T6 powder size solder paste had been tested with Head-In-Pellow (HIP) test procedure to see its oxidation resistance capability. The HIP resistance capability becomes more important when the solder bump change to Cu-Pillar bump in advance SiP package.