Pan Pacific Symposium Conference Proceedings


Direct Bond Interconnect (DBI) For Fine-Pitch Bonding In 3D And 2.5D Integrated Circuits

Authors: Liang Wang *, Gill Fountain, Bongsub Lee, Guilian Gao, Cyprian Uzoh, Scott McGrath, Paul Enquist, Sitaram Arkalgud and Laura Mirkarimi
Company: Invensas Corporation
Date Published: 2/6/2017   Conference: Pan Pacific Symposium


Abstract: Leading-edge technology integration, high-bandwidth and low-power data access call for vertical stacking of semiconductor devices with very fine pitch interconnects. To address this demand, a unique technology referred to as Direct Bond Interconnect (DBI®) which was invented by Ziptronix [1] is being further developed for die to wafer applications. By joining the dielectric regions and the metal interconnect regions on each wafer, DBI can provide both mechanical support and dense electrical interconnects between a wafer pair. Direct Cu-Cu bonding is scalable to the lithography and alignment manufacturing capabilities of any application; DBI was demonstrated at an interconnect pitch of 2 um. With DBI technology, the Under Bump Metallization (UBM), underfill and micro-bumps are replaced with a DBI metallization layer. Bonding at die or wafer level is initiated at room temperature followed by a batch anneal at low temperature and promises to deliver high throughput which is critical for volume manufacturing. This packaging technology enables high performance, low power and small form factor devices in a broad range of applications including mobile, wearable, sensors, data center and telecom.

DBI bonding is demonstrated in both Wafer-to-Wafer (W2W) and Die-to-Wafer (D2W) bonding configurations. The D2W assembly approaches are essential for die stacking and advantageous to sorting wafer for Known- Good-Die and integrating dies of different sizes from different manufacturing lines. The daisy chain structures consist of a face-to-face DBI bond between the bonded wafer to wafer and die to wafer. An electrical test circuit in the redistribution layer (RDL) connects adjacent DBI pads on the same wafer to complete the daisy chain. Multiple test vehicles have been built to evaluate the performance of the technology with various daisy chain designs with different bond pad shapes and sizes (3um to 27um), interconnect pitches (10um to 50um) and chain lengths (2 links to 455k links). The electrical continuity of the daisy chains was probed at both wafer and die. The yield data of the prototype parts ranged from 68 to 98% as we developed the die to wafer bonding process. Non-destructive imaging techniques (Infrared imaging and CSAM) as well as crosssectional imaging have been applied to monitor the bonded interfaces corresponding to the results from electrical test. The resistance of a single DBI bond excluding probe contact resistance was extracted from measurements over a series of chain lengths (2, 20, 200 and 1000 links). For the design of pads in 25um size at 46um pitch, the extracted resistance of a single DBI bond was found 0.238 ohm, close to the theoretical calculated value (0.225 ohm). We disclose a bond pad design approach that is tolerant of large misalignment during die or wafer placement and meets the DBI surface topography and minimum bond time for highthroughput manufacturing requirements. The surface topography of fabricated wafers is measured with white light interferometry and Atomic Force Microscopy (AFM). The correlation of the topology to the design feature, geometry and processing details in key steps such as Chemical Mechanical Planarization (CMP) will be reported in this paper.

Key Words: 

Interconnect, 3D IC, Direct Bond, Hybrid Bond, Wafer-to-Wafer, Die-to-Wafer, Die-to-Die, Fine Pitch, CMP



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