Pan Pacific Symposium Conference Proceedings

Defining A Quality View

Author: Selim S. Nahas
Company: Applied Materials
Date Published: 2/6/2017   Conference: Pan Pacific Symposium

Abstract: The pressure to produce high quality semiconductor devices has never been more demanding. This pressure implies the demand for higher performance packaging, lower cost, smaller form and better integration between front-end-ofline (FEOL) and packaging. When packaging moved into 2.5 and 3D structures, new challenges in the industry prevailed.

With this trend, more collaborative initiative between wafer fabs and Outsourced Semiconductor Assembly and Test suppliers (OSATS) is expected. Non yielding or unreliable die that make it into an assembly stack will inevitably cost substantially more as this invalidates all the other chips in the stack.

A new approach of control is required to handle these changes with the responsibility for much of it moving into the front end. Packaging operations heavily depend on physical geometric tolerances such as planarity and materials adhesion to name a few. To help resolve blind spots that are now causing delivery and reliability difficulties in the industry, this paper explores some new approaches using inline SPC, FDC and electrical test results that may bridge the gap between front end and packaging efforts.

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