Pan Pacific Symposium Conference Proceedings

Reliable Micro-Electronic Assembly Process Design Test Methods - A Non-Standard Approach

Authors: Mike Bixenman, DBA and Mark McMeen, Jason Tynes
Company: Kyzen Corporation and STI Electronics
Date Published: 2/6/2017   Conference: Pan Pacific Symposium

Abstract: Bottom terminated electronic components can fail from contamination trapped under the device. Many devices are designed with large, uninterrupted solder mass and a low standoff height, which close off paths for flux to outgas during reflow. The surface tension effects and wetting properties of the flux within solder paste can underfill the device with active residue that bridges conductive paths. Environmental conditions can mobilize conductive ions that lead to metal migration, and from which ultimately causes intermittent performance and failure.

Non-standard test methods have been developed to perform site specific analysis of both contamination trapped under the bottom termination and reliability expectations based on the current assembly process conditions. These test methods allow an OEM to design a reliable assembly process by testing design factors, the selection of soldering materials, characterizing reflow conditions and cleaning processes.

The purpose of this research paper is to demonstrate the use of these non-standard test methods to design printed circuit board features that allow the flux to outgas during reflow, test both ionic contamination and surface insulation resistance under a site specific component, selection of solder paste, reflow process conditions and optimization of the cleaning process. Data that helps an OEM determine upfront what does not work and the process conditions that do work will provide design conditions for building reliable electronic hardware.

Key Words: 

Bottom Terminated Components, J-STD-001, Flux Residues, Reliability, Warranty, Surface Insulation Resistance

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