IWLPC (Wafer-Level Packaging) Conference Proceedings


Low Cost Electrical Interconnect for 3D Fan Out Wafer Level Packaging

Authors: Ivy Qin, Ph.D., Horst Clauberg, Ph.D., Bob Chylak, Oranna Yauw, and Favian Neo
Company: Kulicke and Soffa Industries, Inc.
Date Published: 10/18/2016   Conference: IWLPC (Wafer-Level Packaging)


Abstract: Fan out wafer level packaging is becoming a key enabler for advanced packages. It brings the advantage of lower package cost that is also thinner than current packages in production and achieves high electrical performance. In combinations these attributes make it a good candidate for mobile applications. Fan Out-based package-on-package (PoP) is being developed that reduces the overall height of an application processor plus memory device from 1.0 mm to 0.8 mm. Lately there has been a push to substantially increase the interconnect density between the top and bottom devices of a PoP package. At these increased interconnect densities, the packages essentially become 3D SiPs. The options for these high-density connection around the periphery of the package are: tall plated Cu pillars, through molded vias (with solder), and Vertical Wires. In this paper the cost of ownership and performance for each of these technologies will be explored and compared. The cost and throughput benefits for the newest of these technologies, Vertical Wire, will be demonstrated. Process flows will be explained. The equipment and materials required to implement this interconnect method will be described along with capability specifications.

Key Words: 

Fan out Wafer Level Package, PoP, Through Mold Interconnection, Wire Bonding, Vertical Wire



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