IWLPC (Wafer-Level Packaging) Conference Proceedings

Ultra Thin Substrate Assembly Challenges For advanced Flip Chip Package

Authors: Fred Lee*, Jianjun Li*, Bindu Gurram* Nokibul Islam, Phong Vu, KeonTaek Kang**, HangChul Choi**
Company: STATS ChipPAC, Inc. *Broadcom Limited **STATS ChipPAC Korea
Date Published: 10/18/2016   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Advanced semiconductor packaging requirements for higher and faster performance in a thinner and smaller form factor continues to grow for mobile, network and consumer devices. While the increase in device input/output (I/O) density is driven by the famous “Moore’s Law”, the packaging industry is experiencing opposing trends for more complex packaging solutions while the expected cost targets are in a downward direction.

Demand for high speed flip chip packages create an opportunity for highly integrated, multi-chip modules (MCM’s) and 2.5D/3D silicon (Si) interposer packages which are emerging very slowly now due to the higher costs often associated with infrastructure and supply chain challenges before a technology is mature. Achieving both increased margins in the power delivery and increased functionality in next generation high speed applications requires extremely efficient, low loss package designs with an ultra thin core or coreless substrate with fine line and space. As the substrate gets thinner, it becomes very flexible and one of the biggest assembly challenges for ultra thin coreless substrates is to keep the substrate flat during the assembly process and maintain yield targets. Other issues with thin substrates are more or less related to post assembly such as handling, long term package reliability and functionality in the application field. The work presented in this paper describes key factors for mitigating several assembly related issues in the manufacturing line, including package warpage/coplanarity, and selecting the optimum processes and materials for such ultra thin coreless substrate flip chip packages with high assembly yields.

A very comprehensive design of experiment (DOE) is being carried out to achieve the objective of the work. A test vehicle has been designed using a flip chip package with ultra thin coreless buildup substrate utilizing various assembly materials and processes. More work will be carried out to expand the scope of the technology for multi chip module (MCM) die and 2.5D integration.

Key Words: 

Flip Chip, Ultra Thin Substrate, Recon, Assembly, Warpage

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