Ultrathin WLFOAuthors: Eoin O`Toole, Steffen Kroehnert, José Campos, Virgilio Barbosa, Leonor Dias
Company: NANIUM S.A.
Date Published: 10/18/2016 Conference: IWLPC (Wafer-Level Packaging)
One of the challenges for the future of semiconductor packaging is reduction of the board level volume real estate occupied by each component. With the drive towards lower profile end user devices incorporating large display area and battery life the three dimensional available for semiconductor packages is diminishing. It is well known that WLFO single die packaging but even more significant system integration enables the shrinkage of the XY footprint of the package through flexible very dense heterogeneous system-in-package integration . But one of the disruptive advantages of the substrate-less WLFO technology is to also permit significant reduction of the overall package height (Z). A total package height for a BGA package including solder balls <500um and for a LGA package with solder land pads only <300um is achievable today, and further development towards even thinner packages is on the way.
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