IWLPC (Wafer-Level Packaging) Conference Proceedings

Understanding and Solving The Challenges of Chip To Package Co-Design For Fo-WLP

Author: Bill Acito
Company: Cadence Design Systems
Date Published: 10/18/2016   Conference: IWLPC (Wafer-Level Packaging)

Abstract: Fan-out, arguably the fastest-growing advanced packaging technology, will continue to grow at a CAGR of 55% for a $2.4B market by 2020 (ref: Yole Dev), driven predominately by mobile processing and wireless. These designs can contain single large die, or multiple die, yet are limited in the number of available routing layers. Without the benefit of larger layer counts and with substrates not much larger than the die constituents, providing the ability to plan and optimize the I/O pad ring of the die in the design can significantly and positively impact the ability to provide a routable solution. This paper will discuss the challenges of designing a large FO-WLP device, as well as the capabilities required to plan, optimize, and implement the die I/O floor plan and optimize the interconnect in the design in as few layers as possible. We will discuss the challenges at each phase of the design: from initial system planning (path-finding) and feasibility, I/O pad ring optimization, assignment, early SI analysis, optimization and implementation, and finally sign-off SI/PI analysis and artwork DRC signoff.

Key Words: 

Co-Design, FOWLP, System Planning, Path-Finding, EDA, Package

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