IWLPC (Wafer-Level Packaging) Conference Proceedings


Cost Analysis of Die Assembly For 2.5D and 3D Packaging

Authors: Chet A Palesko and Amy P Lujan
Company: SavanSys Solutions LLC
Date Published: 10/18/2016   Conference: IWLPC (Wafer-Level Packaging)


Abstract: In spite of the relatively high cost, 2.5D and 3D packaging can provide significant size and performance advantages over other packaging technologies. Products such as high end FPGAs, high performance GPUs, and high bandwidth memory are target applications for these technologies, but none have the volume requirements of mobile phones and tablets. Without high volume to drive changes, future cost reduction will only result from progress on individual activities in the 2.5D and 3D manufacturing process. One of the significant cost drivers for 2.5 and 3D packaging is the die assembly cost.

This paper will provide focused cost analysis of the 2.5D and 3D die assembly process. The cost and yield of current assembly technologies will be analyzed, including the impact on the total packaging cost. Assembly cost improvements will be evaluated to understand the potential savings associated with increasing die assembly throughput, increasing the process yield, and using wafer-to-wafer assembly.

Key Words: 

2.5D Packaging, 3D, Cost, Die Bonding



Members download articles for free:

Not a member yet?

What else do you get when you join SMTA? Read about all of the benefits that go along with membership.

Notice: Sharing of articles is restricted to just your immediate work group. Downloaded papers should not be stored on an external network or shared on the internet.


Back


SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344 USA

Phone +1 952.920.7682
Fax +1 952.926.1819