IWLPC (Wafer-Level Packaging) Conference Proceedings

TSV Assembly: Package Architectures and Trade-offs

Authors: Paul Silvestri, Rama Alapati, Mike Kelly
Company: Amkor Technology, Inc.
Date Published: 10/18/2016   Conference: IWLPC (Wafer-Level Packaging)

Abstract: The proliferation of connected devices is driving higher system performance requirements. Metrics such as form-factor, data transfer rate, signal integrity, memory bandwidth, and thermal capability are considerations for improving system performance. In addition, technology scaling limitations present a cost barrier to traditional semiconductor die shrinks and device integration using 2D packaging techniques. Through Silicon Via (TSV) packaging technology enables homogenous and heterogeneous integration of logic and memory co-located closely together in a small form-factor assembly. High-density signal routing and very high bump counts are driving line and space widths with very fine pitch interconnects using copper pillar technology on interposers.

Many of these systems require gigabytes of high-bandwidth DRAM memory. Several types of these memories have been deployed but the most widely adopted memory is High Bandwidth Memory (HBM). This JEDEC-defined memory uses TSV interconnects to stack DRAM core layers on top of a control layer. The new memory standard describes four or eight DRAM layers sitting on top of a control layer. The resulting device is a small-body, Wafer Level Chip Scale Package (WLCSP) memory with more than 2K fine pitch bumps and very high count TSV interconnects. The memory cube (HBM) is assembled onto a TSV-baring silicon interposer and co-located near the logic device using high density wiring and fine-pitch copper pillars. The interposer is fabricated with several layers of micron and sub-micron wiring for die-to-die interconnect and TSV interconnect for die to printed circuit board (PCB) assembly.

Because of the close proximity of the logic and memory components, power density is increasing rapidly. Thermal management must be deployed to limit the junction temperature (Tj) specifications for both logic and memory technology (typically, 105°C and 95°C, respectively).

In traditional 2D module integration, logic and memory components are fully tested in their packaged, discrete form prior to multi-chip module (MCM) assembly, so incoming yields can be managed with acceptable results. However, in TSV systems, logic and memory components are integrated into the package with only limited opportunities for test. Test support is often limited to wafer-probe style testing until the assembly is sufficiently completed to a point where traditional socket testing can be performed. Without sufficient test capability, logic and memory components in one region of an assembly can be affected due to defects in an adjacent region.

With the physical requirements of the interconnects, new materials and methodologies must be deployed that provide high reliability. In essence, co-design of the interposer, logic, memory, and package is required along with appropriate assembly and test methodologies. When selecting the optimum TSV packaging technology and floor planning, all of these key parameters should be considered.

This paper describes TSV assembly considerations whether integrating in 3D or 2.5D packages for next generation mobile, high performance graphics, and networking applications.

Key Words: 

Through Silicon Via, TSV, 3D, 2.5D, Chip on Wafer, CoW, Chip on Substrate, CoS, Interposer, Wafer Level Chip Scale Package, WLCSP

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