Electroplated Nano Twinned Copper For Wafer Level Packaging
Authors: Stream Chung, Ph.D., Zong-Cyuan Chen, and Yao-Zong Chen and Yi-Cheng Chu, Kuan-Ju Chen, Chih-Han Tseng, and Chih Chen, Ph.D. Company: Chemleader Corporation and Dept. of Materials Sci. & Eng., National Chiao Tung University Date Published: 10/18/2016
IWLPC (Wafer-Level Packaging)
Abstract: Electroplated copper has been extensively used in wafer level packaging interconnect material such as copper pillar and redistribution line (RDL). For the past decade, plating chemistry development focused on cost reduction and geometry control, for example, plating speed, plating thickness uniformity, and bump shape control. When the packaging scheme moves to fine pitch to support higher bandwidth, material property becomes the challenge moving forward. Nano twinned copper with unidirectional grain texture on (111) plane from DC plating shows promising potential for the next generation package. Copper-to-copper direct bond in 3D IC package and fine line RDL in fan-out package are two examples. Copper-to-copper direct bond is identified as the solution of bumpless microjoints when stacking between chips, but one of the bottle neck is the high bonding temperature. By applying unidirectional (111) nano twinned copper, the bonding temperature could be reduced to 150°C at low vacuum environment from the high surface diffusion rate on (111) plane. As for fine line RDL in fan-out package, when L/S shrinks to 2/2 µm, the thermal expansion coefficient mismatch between silicon and molding compound introduces significant stress to RDL line, and results in crack failure during thermal cycling test. Copper strengthened by high density nano twins offers over 400MPa in ultimate tensile strength, and its strength remains high after multiple thermal anneal at polyimide curing temperature 230°C. High density nano twins contribute superior strength and thermal stability.