IWLPC (Wafer-Level Packaging) Conference Proceedings


A Practical Approach to Test Through Silicon Vias (TSV)

Author: Gerard John
Company: Amkor Technology Inc.
Date Published: 10/18/2016   Conference: IWLPC (Wafer-Level Packaging)


Abstract: There is increased interest in developing packaging solutions that provide higher bus speeds at reduced power per bit ratios. This has driven designers to look for techniques that shorten the distance between chips (reducing drive currents) and use wider data busses (finer line-space traces) resulting in the growth of two and a half dimension (2.5D), and three dimensional (3D) packages. While much of the effort and attention has focused on the development of processes and technologies to build Through Silicon Vias (TSVs), the industry has lagged behind in developing test strategies to qualify these designs.

Electrical testing of TSVs can only be performed after back grind and etch processes expose the TSVs - a task that is usually performed at the Outsourced Assembly, and Test (OSAT) supplier, see Figure 1. Therefore, when a TSV interposer wafer leaves the foundry, the quality of the TSVs remains unknown until it is processed at the OSAT.

Within a package, the functions of the TSVs can vary widely. Basically, they may be used to carry DC current to power the chip or carry high-speed signals for input /output (I/O) pins or provide low-impedance paths which connect the die to the ground plane. Based on their functions, specific tests need to be performed to verify TSV functionality. Furthermore, TSVs need to undergo characterization tests such as stress and electro-migration to quantify their long-term reliability.

This paper analyzes the different kinds of tests that should be performed on TSVs during the design, qualification and production phases. It provides a case study to an interposer vendor qualification and analyzes the data collected in the process through various laboratory experiments. Additionally, it also discusses the practical challenges faced while testing TSVs on thinned wafers, including the limitations of equipment and probe card capability.

Key Words: 

Through Silicon Via, TSV, Test, OSAT, TSV Redundancy



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